Patents by Inventor Tadaomi Sakurai

Tadaomi Sakurai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device manufacturing method permitting suppression of leak current through the PN junction
    Patent number: 6551882
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: April 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa
  • Semiconductor device having a memory cell region and peripheral circuit region and method of manufacturing the same
    Patent number: 6339237
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: January 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa
  • Semiconductor device and method of manufacturing the same
    Publication number: 20010010390
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Application
    Filed: March 27, 2001
    Publication date: August 2, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa