Patents by Inventor Tadashi Arakawa
Tadashi Arakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123332Abstract: A shooting game control method, which is executed by a computer incorporated in a device including a display and a touch panel, includes accepting a touch operation on the touch panel; displaying a first frame indicative of a shooting effective range on the display in accordance with a position of the touch operation; accepting an instruction for an attack on an attack target in a state in which the first frame is displayed; determining whether the attack target in a game image displayed on the display is within the first frame or not, at a time point when the instruction for the attack has been accepted; and controlling the attack on the attack target in the game image in accordance with a result of the determining.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Applicant: GREE, INC.Inventors: Yuichi TSUCHIYA, Norihiro SAWADA, Tadashi NAGANO, Takeshi ARAKAWA
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Patent number: 8364730Abstract: In response to a write command with regard to an FAT1 area received from a host device, the data storage apparatus collectively records management information with regard to the FAT1 area simultaneously with duplicate management information of identical content as management information with regard to an FAT2 area at consecutive addresses. In response to a write command with regard to the FAT2 area received from the host device subsequent to the write command with regard to the FAT1 area, the data storage apparatus notifies the host device of completion of data writing without recording the management information with regard to the FAT2 area. This arrangement effectively enhances the data writing efficiency in the data storage apparatus having multiple records of identical management information.Type: GrantFiled: May 11, 2007Date of Patent: January 29, 2013Assignee: Buffalo Inc.Inventor: Tadashi Arakawa
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Patent number: 8136015Abstract: In the ordinary operation mode, a data storage apparatus writes data into a first flash memory, while writing ECC data, which is used for correcting the data written in the first flash memory, into a second flash memory. When there is no remaining storage space in the first flash memory, the data storage apparatus deletes existing ECC data previously written in the second flash memory and writes ordinary data into the second flash memory. This arrangement enhances the reliability of data and enables effective use of the original storage space in the system of data storage with multiple storage areas.Type: GrantFiled: May 14, 2007Date of Patent: March 13, 2012Assignee: Buffalo Inc.Inventors: Noboru Kawai, Tadashi Arakawa
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Patent number: 7979627Abstract: A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory.Type: GrantFiled: May 13, 2008Date of Patent: July 12, 2011Assignee: Buffalo Inc.Inventor: Tadashi Arakawa
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Publication number: 20090164538Abstract: A data storage apparatus comprises a USB connector, a USB control circuit, a flash controller, and a flash memory. After the process of formatting the data storage apparatus by a host device, the flash controller forcibly rewrites FAT number data recorded in a bios parameter block area from ‘2’ to ‘1’ at the time of restoration of power supply. Such rewriting of the FAT number data causes the host device to identify the presence of only one FAT area. This arrangement desirably improves the data writing efficiency of the data storage apparatus configured to generate multiple management tables in the formatting process by the host device.Type: ApplicationFiled: May 11, 2007Publication date: June 25, 2009Applicant: BUFFALO INC.Inventor: Tadashi Arakawa
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Publication number: 20090158124Abstract: In the ordinary operation mode, a data storage apparatus writes data into a first flash memory, while writing ECC data, which is used for correcting the data written in the first flash memory, into a second flash memory. When there is no remaining storage space in the first flash memory, the data storage apparatus deletes existing ECC data previously written in the second flash memory and writes ordinary data into the second flash memory. This arrangement enhances the reliability of data and enables effective use of the original storage space in the system of data storage with multiple storage areas.Type: ApplicationFiled: May 14, 2007Publication date: June 18, 2009Applicant: Buffalo Inc.Inventors: Noboru Kawai, Tadashi Arakawa
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Publication number: 20090132620Abstract: In response to a write command with regard to an FAT1 area received from a host device, the data storage apparatus collectively records management information with regard to the FAT1 area simultaneously with duplicate management information of identical content as management information with regard to an FAT2 area at consecutive addresses. In response to a write command with regard to the FAT2 area received from the host device subsequent to the write command with regard to the FAT1 area, the data storage apparatus notifies the host device of completion of data writing without recording the management information with regard to the FAT2 area. This arrangement effectively enhances the data writing efficiency in the data storage apparatus having multiple records of identical management information.Type: ApplicationFiled: May 11, 2007Publication date: May 21, 2009Applicant: BUFFALO INC.Inventor: Tadashi Arakawa
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Publication number: 20080288716Abstract: A storage device includes: a binary flash memory that has a first storage area and a capacity of storing two values per each cell; a multivalued flash memory that has a second storage area and a capacity of storing at least three values per each cell; and a controller configured to arrange the first storage area ahead of the second storage area, logically combine the first storage area with the second storage area to form a single combined storage area, and perform data reading and data writing from and into the combined storage area. Data management information is stored in a head of the combined storage area according to a predetermined file system. The storage device of this arrangement has the advantages of both an SLC flash memory and an MLC flash memory.Type: ApplicationFiled: May 13, 2008Publication date: November 20, 2008Applicant: BUFFALO INC.Inventor: Tadashi ARAKAWA
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Patent number: 6130885Abstract: In a wireless communication apparatus for communicating by using a frequency hopping system, by providing a function such that frequency channels are divided into a plurality of channel groups or data of different types is transmitted every divided channel group or a different channel access system is used every channel group, even if the data of different types is simultaneously transmitted, a data error due to a collision or mutual interference of the data is prevented.Type: GrantFiled: March 18, 1996Date of Patent: October 10, 2000Assignee: Canon Kabushiki KaishaInventors: Michihiro Izumi, Tadashi Arakawa, Yasunori Suzuki
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Patent number: 5430853Abstract: A DMA transfer control system includes a DMA control unit connected to a bus shared by a CPU; a storage device for receiving and storing various parameters of the DMA control unit via the CPU; an addressing unit for outputting an address of the various parameters to be set at the DMA control unit; and a circuit for outputting the various parameters from the storage device to the DMA control unit in synchronism with a reference clock of the CPU.Type: GrantFiled: March 10, 1993Date of Patent: July 4, 1995Assignee: Canon Kabushiki KaishaInventor: Tadashi Arakawa
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Patent number: 5408610Abstract: First, second and third communication control apparatus are arranged in a logic ring, with management information, such as address information, being transmitted in a data packet transmitted around the ring. When the received packet data includes management information of the apparatus that has just received it, that information is deleted. On the other hand, when the received packet data does not include management information of the receiving apparatus, management information of the receiving apparatus is added to the packet data. In this way, the management information can be updated for all the apparatus in a simple fashion and in a short amount of time.Type: GrantFiled: February 17, 1993Date of Patent: April 18, 1995Assignee: Canon Kabushiki KaishaInventor: Tadashi Arakawa
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Patent number: 4780871Abstract: A data transmission system for causing one of a plurality of nodes commonly connected to a transmission line to obtain a transmission right by a token as a transmission right assignment instruction. The system includes at least one master node which stores and renews the number of transmission requests that cannot be previously processed. Upon reception of the transmission right by the master node by means of the token, the master node sends a token to assign the transmission right to a slave node having the largest number of transmission requests that could not be previously processed. Otherwise, the master node sends a token to assign the transmission right to a normal downstream slave node to be assigned with the token.Type: GrantFiled: July 8, 1986Date of Patent: October 25, 1988Assignee: Canon Kabushiki KaishaInventor: Tadashi Arakawa