Abstract: The invention provides a method for producing radiolabeled tyrosine derivatives with good purity and stability, by a safe method suitable for industrial production of pharmaceuticals. The invention relates to a method for producing Compound (5) and Radiolabeled Compound (6) as follows: wherein each symbol is as defined in the description.

Abstract: A semiconductor device includes a MOSFET having: a gate electrode provided over a silicon substrate; and a first impurity diffusion region and a second impurity diffusion region provided in the silicon substrate in different sides of said first gate electrode, wherein the MOSFET has an extension region in an upper section of the first impurity diffusion region and no extension region in an upper section of the second impurity diffusion region, and has a first silicide layer over the first impurity diffusion region and has no silicide layer over the second impurity diffusion region in vicinity of a side edge of the gate electrode.

Abstract: The semiconductor device includes a plurality of transistors at least having different channel widths from each other. Threshold voltages of those transistors are set to be substantially equal to each other, by using both of substantially the same channel dose for each of those transistors, and work function control using a predetermined metal to be deposited on a gate insulating of those transistors and/or a gate electrode material of each of those transistors (that is, work function control based on a gate structure (gate insulating film and/or gate electrode) with respect to a channel region of each of those transistors).

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Abstract: A semiconductor device is provided which is capable of preventing corrosion of circuit portion and ensuring high reliability by optimizing a construction of outer-surrounding protecting walls that surround an internal element region to completely stop invasion of water from an edge portion of a semiconductor chip. The outer-surrounding protecting walls made up of a wiring layer and a via layer are formed in a manner to surround the internal element region and that a distance between an edge portion of the semiconductor chip and the outermost-surrounding protecting wall is 30 &mgr;m. The outer-surrounding protecting wall is so formed as to doubly or more surround the internal element region.

Abstract: In a semiconductor device, a circuit unit is formed in an inside portion, and seal rings that enclose the inside portion that are composed of walls of metal layers are formed around the periphery. In the corners, the seal rings include linear parts that extend inwardly in addition to the linear parts that extend along the periphery, whereby the seal rings are formed in a planar pattern having small rectangular planar patterns in each corner.

Abstract: In the semiconductor device of the present invention, a plurality of dummy patterns are formed in a grid arrangement in the scribe line areas of a wafer, and a plurality of dummy patterns are formed in a diagonally forward skipped arrangement in the chip interior areas of the wafer. Altering the arrangement of dummy patterns in the chip interior areas and scribe line areas in this way enables formation of dummy patterns with greater uniformity in the chip interior areas and enables formation of dummy patterns with greater resistance to loss that occurs when dicing in scribe line areas.

Abstract: In a method of manufacturing a semiconductor device, MOS transistors are formed on a semiconductor substrate. Each of the MOS transistors includes impurity diffusion regions and a gate electrode. A first interlayer insulating film is deposited over the MOS transistors. Contact holes are opened in the first interlayer insulating film so as to reach the impurity diffusion regions. A conductor is deposited on an entire surface of the semiconductor substrate. The deposited conductor is etched back in order to form contact plugs only in the contact holes. Pad portions are formed only on the contact plugs by the use of a selective growth method. A capacitor is formed over the semiconductor substrate so as to be connected to the pad potions via capacitor contacts.

Abstract: The present invention discloses a semiconductor device, and a manufacturing method thereof, which is obtained by forming a logic circuit part capable of performing a high speed arithmetic processing and memory cell part of a DRAM having a high information holding characteristic, on the same substrate.

Abstract: The invention relates to an improvement in formation of a gate electrode. In the invention, there are formed first and second oxides on a surface of a substrate. The second oxides have a top surface higher by a height H than top surfaces of the first oxides. A gate electrode composed of a polysilicon film and a silicide film deposited on the polysilicon film is formed so that the polysilicon film is planarized at a level higher than top surfaces of the first oxides but lower than top surfaces of the second oxides. The invention prevents excessive etching of the polysilicon film without fabrication steps being increased, and thus makes it possible to form a gate electrode having a dimension defined by a mask.

Abstract: In a semiconductor memory, for forming a storage node of an information storage capacitor formed above a semiconductor substrate, an interlayer insulator film is formed above the semiconductor substrate, and a contact hole is formed to penetrate through the interlayer insulator film and to reach the semiconductor substrate. A polysilicon film is deposited to fill the contact hole and to cover the interlayer insulator film, and ions are implanted into the polysilicon film to convert a surface layer of the polysilicon film into an amorphous state, so that the surface of polysilicon film is smoothened. On the polysilicon film, a resist mask for patterning of the storage node is formed by a photolithography, and, and the polysilicon film is etched using the resist mask to form the storage node.

Abstract: A plurality of gate electrodes are formed over a semiconductor substrate. An etching stopper layer is formed on these plurality of gate electrodes. Sidewall layers are formed on the side faces of the plurality of gate electrodes. An interlayer insulating film covering the plurality of gate electrodes and the sidewall layers is formed. A contact hole is formed in the interlayer insulating film among the plurality of gate electrodes. Here, the contact hole is formed in the interlayer insulating film by making the etching rate of the etching stopper film lower than the etching rate of the interlayer insulating film and the etching rate of the sidewall layer substantially equivalent to or higher than the etching rate of the interlayer insulating film.

Abstract: A method of manufacturing a semiconductor integrated circuit device which stores information by storing charges in a capacitor portion formed on a semiconductor substrate is provided. This method includes the steps of depositing a conductive film for forming a lower electrode of storage node capacitor portion on an insulating interlayer film formed with a contact hole for forming a contact that connects the capacitor portion with the substrate, depositing a cap oxide film on the conductive film and planarizing the cap oxide film, applying a resist on the planarized cap oxide film to a uniform thickness and forming a pattern mask of the storage node capacitor portion from the resist, etching the cap oxide film and the conductive film by using the pattern mask as a mask, and forming a lower electrode of the storage node capacitor portion by removing the cap oxide film.

Abstract: In a method for manufacturing a capacitor, a lower electrode is formed by an amorphous refractory metal silicide layer and its underlying conductive layer, a heating operation is performed upon the amorphous refractory metal silicide layer, so that the amorphous refractory metal silicide layer is converted into a polycrystalline refractory metal layer having an uneven surface.

Abstract: An intermediate insulation layer provided between a wiring of gate electrodes on a semiconductor substrate and a wiring formed in an upper layer includes a first interlayer insulation layer, a silicon rich oxide layer stacked on the first interlayer insulation layer and containing excessive silicon atom, and a second interlayer insulation layer stacked over the silicon rich oxide layer. Processes are provided for selectively performing dry etching for the insulation layers in order to simultaneously and easily form a self-aligned type contact hole on the diffusion layer position at the gap between oppositely arranged gate electrodes and a contact hole on the wiring of the predetermined gate electrode. In this manner, on the diffusion layer and the wiring of the gate electrode, the self-align contact hole and the contact hole are formed in the same process. This permits elimination of the need for margins in formation of the contact hole in the semiconductor device adapted for ultra-high packing density.

Abstract: At the surface of a semiconductor substrate a conductor film over a silicon comprising insulating film, and the first aluminium oxide film are formed. These films are patterned to form a plurality of lines and an aluminium oxide film mask covering the top faces of the lines. Over the whole surface, the second aluminium oxide film is formed and etched back to form aluminium oxide film spacers covering the side faces of the lines. Over the whole surface a silicon oxide comprising dielectric film is formed. Anisotropic dry etching of the dielectric film and the insulating film is performed with fluorocarbon comprising gas to form self-aligned contact holes extending down to the surface of diffused layers formed at the surface of the semiconductor substrate.