Abstract: The basic cell design method of the present invention is a method for carrying out: extended pattern formation for extending the patterns of input wiring and output wiring in the longitudinal direction, forming first extended patterns that extend with a prescribed dimensional width in a direction perpendicular to the longitudinal direction at the ends of the extended patterns, and forming second extended patterns that extend with the prescribed dimensional width from the input wiring and the output wiring at the center of the cell in the longitudinal direction; and dummy pattern formation for subsequently arranging dummy patterns in vacant areas within the cell.

Abstract: In a semiconductor device including an upper-layer wiring and a lower-layer wiring that overlaps the upper-layer wiring, an wiring switching option includes a via extending from the upper-layer wiring toward the lower-layer wiring. The wiring switching option switches a wiring connection state according to whether the via extends from the upper-layer wiring to reach the lower-layer wiring or extends from the upper-layer wiring to terminate in between the upper-layer wiring and the lower-layer wiring.

Abstract: A configuration is provided with: memory cell arrays, sense amplifiers, bit lines that connect the memory cells and sense amplifiers, and transfer gates that are inserted on the bit lines for ON/OFF control of the connections of the memory cells and the sense amplifiers; wherein the sense-amplifier-interior bit lines, which are the sense-amplifier sides of the bit lines from the transfer gates, are arranged at positions interposed between exterior bit lines, which are the memory-cell side of the bit lines from the transfer gates.

Abstract: The basic cell design method of the present invention is a method for carrying out: extended pattern formation for extending the patterns of input wiring and output wiring in the longitudinal direction, forming first extended patterns that extend with a prescribed dimensional width in a direction perpendicular to the longitudinal direction at the ends of the extended patterns, and forming second extended patterns that extend with the prescribed dimensional width from the input wiring and the output wiring at the center of the cell in the longitudinal direction; and dummy pattern formation for subsequently arranging dummy patterns in vacant areas within the cell.

Abstract: A configuration is provided with: memory cell arrays, sense amplifiers, bit lines that connect the memory cells and sense amplifiers, and transfer gates that are inserted on the bit lines for ON/OFF control of the connections of the memory cells and the sense amplifiers; wherein the sense-amplifier-interior bit lines, which are the sense-amplifier sides of the bit lines from the transfer gates, are arranged at positions interposed between exterior bit lines, which are the memory-cell side of the bit lines from the transfer gates.

Abstract: A semiconductor device is provided comprising a capacitance adjustment section which enables the free setting of the amount of adjustment of a wiring capacitance, and for which the adjustment operation can be carried out simply. The semiconductor device comprises a capacitance adjustment section which is provided with a capacitance adjustment wiring which is connected to a target wiring for capacitance adjustment for adjusting wiring capacitance, and a constant voltage wiring which is formed on the same layer as the capacitance adjustment wiring and to which is applied a constant voltage. The capacitance adjustment wiring and the constant voltage wiring are positioned proximately and form a predetermined line capacitance, and this line capacitance is used to adjust a wiring capacitance of the target wiring for capacitance adjustment.

Abstract: In a semiconductor integrated circuit including a plurality of standard cells which are arranged in an array direction to constitute a logic circuit and which are supplied with a clock signal, each of the standard cells has a first side and a second side opposite to each other and extending in the array direction, and a clock signal terminal for receiving the clock signal is provided on only the first side of each of the standard cells. In each of the standard cells, there exists no internal interconnection which is used to supply the clock signal within the standard cell and which reaches the second side of the standard cell.

Abstract: An inverter is connected between an external GND terminal and a drain of an internal circuit such that the drain of the internal circuit is not directly connected to the external GND terminal. As a result, even when the input of a transfer gate of the internal circuit is to be at a GND level, it is possible to prevent any current flowing to VDD from the drain of a p-type transistor through a well and to prevent electrons from flowing into an external power supply potential VDD terminal from the drain of an n-type transistor. Thus, the internal circuit can be protected from ESD even when static electricity is applied to an external power supply terminal or GND terminal.