Patents by Inventor Tadashi Miyasaka

Tadashi Miyasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240145465
    Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.
    Type: Application
    Filed: December 14, 2023
    Publication date: May 2, 2024
    Inventors: Shigeki SATO, Seiji MOMOTA, Tadashi MIYASAKA
  • Patent number: 11855077
    Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: December 26, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shigeki Sato, Seiji Momota, Tadashi Miyasaka
  • Publication number: 20190267370
    Abstract: A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.
    Type: Application
    Filed: December 21, 2018
    Publication date: August 29, 2019
    Inventors: Shigeki SATO, Seiji MOMOTA, Tadashi MIYASAKA
  • Publication number: 20090166851
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Application
    Filed: March 2, 2009
    Publication date: July 2, 2009
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Publication number: 20050218426
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Application
    Filed: June 2, 2005
    Publication date: October 6, 2005
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 6914325
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 5, 2005
    Assignee: Fuji Electric Co. Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 6905063
    Abstract: A semiconductor device can be formed with fewer voids in the solder bonding a laminate of a silicon chip, an insulator substrate, and a metal base, with a solder layer positioned between the layers. After placing the laminate in a furnace, it is evacuated and then pressurized with hydrogen gas, and then heated to melt the solder. While maintaining the heat, the furnace is again evacuated to remove voids in the solder, and then the furnace is positively pressurized again with hydrogen gas to prevent holes produced by the voids traveling in the solder, and to obtain a uniform solder fillet shape. Thereafter the laminate is rapidly cooled to obtain a finer grain solder to increase the rate of creep to quickly remove the warping of the laminate to the original state.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: June 14, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Akira Morozumi, Tadashi Miyasaka, Katsumi Yamada, Eiji Mochizuki
  • Patent number: 6690087
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Grant
    Filed: December 28, 2001
    Date of Patent: February 10, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Publication number: 20040017005
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Application
    Filed: July 18, 2003
    Publication date: January 29, 2004
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Publication number: 20030222126
    Abstract: A semiconductor device can be formed with fewer voids in the solder bonding a laminate of a silicon chip, an insulator substrate, and a metal base, with a solder layer positioned between the layers. After placing the laminate in a furnace, it is evacuated and then pressurized with hydrogen gas, and then heated to melt the solder. While maintaining the heat, the furnace is again evacuated to remove voids in the solder, and then the furnace is positively pressurized again with hydrogen gas to prevent holes produced by the voids traveling in the solder, and to obtain a uniform solder fillet shape. Thereafter the laminate is rapidly cooled to obtain a finer grain solder to increase the rate of creep to quickly remove the warping of the laminate to the original state.
    Type: Application
    Filed: March 26, 2003
    Publication date: December 4, 2003
    Applicant: FUJI Electric Co., Ltd.
    Inventors: Akira Morozumi, Tadashi Miyasaka, Katsumi Yamada, Eiji Mochizuki
  • Publication number: 20020109152
    Abstract: A power semiconductor module has a circuit assembly body, which includes a metal base, a ceramic substrate, and a power semiconductor chip, and is combined with a package having terminals formed integrally. The ceramic substrate of the module has a structure such that an upper circuit plate and a lower plate are joined to both sides of a ceramic plate, respectively, and the metal base and the ceramic substrate are fixed to one another using solder, thereby improving reliability and lengthening a life of a power semiconductor module by optimizing a ceramic substrate and a metal base thereof, the dimensions thereof, and material and method used for a join formed between the ceramic substrate and metal base.
    Type: Application
    Filed: December 28, 2001
    Publication date: August 15, 2002
    Inventors: Takatoshi Kobayashi, Tadashi Miyasaka, Katsumi Yamada, Akira Morozumi
  • Patent number: 5561393
    Abstract: A control device for controlling a double gate semiconductor device having a second gate electrode for controlling transition from a thyristor operation to a transistor operation, and a first gate electrode for controlling transition from transistor operation to an ON/OFF operation, and for controlling a current passing from a collector electrode to an emitter electrode, includes a first gate control circuit for delaying a turn-off signal to the double gate semiconductor device and applying the turn-off signal to the first gate electrode.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: October 1, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ken'ya Sakurai, Masahito Otsuki, Noriho Terasawa, Tadashi Miyasaka, Akira Nishiura, Masaharu Nishiura
  • Patent number: 5500619
    Abstract: A semiconductor device includes a main insulated gate type switching element having a gate electrode and controllable by a gate voltage applied to the gate electrode, a current detecting insulated gate type switching element connected in parallel to the main insulated gate type switching element, a detecting resistor for detecting a current flowing in the current detecting insulated gate type switching element, a gate controlling element capable of controlling the gate voltage by a drop voltage in the detecting resistor, and a gate control relieving element for relieving a varying speed of the gate voltage varied based on an operation of the gate controlling element.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: March 19, 1996
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tadashi Miyasaka
  • Patent number: 5461060
    Abstract: The disclosure concerns pyrimidine derivatives represented by the following general formulas [I] and [I'] and having antiviral activity, particularly antiretroviral activity such as anti-HIV activity: ##STR1## and pharmaceutical compositions having antiviral activity and comprising the above-described derivative(s) as an active ingredient.
    Type: Grant
    Filed: September 3, 1993
    Date of Patent: October 24, 1995
    Assignee: Mitsubishi Kasei Corporation
    Inventors: Tadashi Miyasaka, Hiromichi Tanaka, Erik D. A. De Clercq, Masanori Baba, Richard T. Walker, Masaru Ubasawa
  • Patent number: 5459339
    Abstract: A semiconductor device thyristor structure includes a first conductive type collector region, second conductive type and first conductive type base regions, and a second conductive type emitter region. First conductive type regions and second conductive type regions have respective first and second type majority carriers. A first MOSFET injects the second type majority carriers into the second conductive type base region. A second MOSFET is opened and closed independent of the first MOSFET and extracts the first type majority carriers from the first conductive type base region. A third MOSFET has a first gate electrode which is also a gate electrode of the first MOSFET, for extracting the first type majority carriers from the first conductive type base region. First conductive type and second conductive type emitter regions are formed within the first conductive type base region and an emitter voltage can be simultaneously applied to these emitter regions.
    Type: Grant
    Filed: April 29, 1993
    Date of Patent: October 17, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ken'ya Sakurai, Masahito Otsuki, Noriho Terasawa, Tadashi Miyasaka, Akira Nishiura, Masaharu Nishiura
  • Patent number: 5343098
    Abstract: A snubber circuit, for absorbing voltage spikes applied to a power semiconductor device used as a switching means, utilizes the junction capacitance of a directly connected semiconductor device, thereby avoiding the need for a separate high-voltage capacitor. Embodiments shown use either a MOSFET or a bipolar transistor with a resistor connected in parallel between the gate (base) and the source (emitter) of the MOSFET (or bipolar transistor.) The snubber circuit of the present invention may also be a module integrally formed on a radiating base of the power semiconductor device.
    Type: Grant
    Filed: December 7, 1990
    Date of Patent: August 30, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tadashi Miyasaka
  • Patent number: 5318972
    Abstract: A pyrimidine nucleoside derivative and pharmaceutically acceptable salt thereof specified by the presence of ethyl group or isopropyl group at 5-position of the pyrimidine ring and the presence of a (substituted) phenylthio or a (substituted) benzyl group at 6-position of the pyrimidine ring is provided. The pyrimidine nucleoside derivative and pharmaceutically acceptable salt thereof show a markedly higher anti-retroviral activity than conventional analogous compounds and have a relatively low toxicity against the host cells, and therefore, are useful as an active ingredient of antiviral agent.
    Type: Grant
    Filed: March 28, 1991
    Date of Patent: June 7, 1994
    Assignee: Mitsubishi Kasei Corporation
    Inventors: Tadashi Miyasaka, Hiromichi Tanaka, Erik D. A. De Clercq, Masanori Baba, Richard T. Walker, Masaru Ubasawa
  • Patent number: 5287023
    Abstract: In a reverse-bias control circuit for a voltage-driven switching element which turns on upon receiving a forward-bias voltage and turns off upon receiving a reverse-bias voltage, a step-down circuit is included which serves for stepping down a reverse-bias voltage after a time delay which is substantially equal to the turn-off delay of the voltage-driven switching element. The control circuit further includes a recovery circuit for stopping operation of the step-down circuit after a delay which is substantially equal to the total turn-off time of the voltage-driven switching element. The reverse-bias control circuit serves to reduce the reverse-bias voltage, thereby blocking surge-voltage disturbances, without increasing the turn-off delay time.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: February 15, 1994
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Tadashi Miyasaka
  • Patent number: 5112835
    Abstract: 6-substitutted acyclopyrimidine nucleoside derivatives represented by the following general formula I: ##STR1## wherein R.sup.1 represents a hydrogen or halogen atom or a group of alkyl, alkenyl, alkynyl, alkylcarbonyl, arylcarbonyl, arylcarbonylalkyl, arylthio or aralkyl; R.sup.2 represents a group of arylthio, alkylthio, cycloalkylthio, aryl sulfoxide, alkyl sulfoxide, cycloalkyl sulfoxide, alkenyl, alkynyl, aralkyl, arylcarbonyl, arylcarbonylalkyl or aryloxy; R.sup.3 represents a hydroxyalkyl group of which alkyl portion may contain an oxygen atom; X represents an oxygen or sulfur atom or amino group; Y represents an oxygen or sulfur atom; and A represents .dbd.N-- or --NH-- or pharmaceutically acceptable salts thereof, processes for their preparation and antiviral agents containing them as active ingredients.
    Type: Grant
    Filed: November 21, 1989
    Date of Patent: May 12, 1992
    Assignee: Mitsubishi Kasei Corporation
    Inventors: Tadashi Miyasaka, Hiromichi Tanaka, Erik D. A. De Clercq, Masanori Baba, Richard T. Walker, Masaru Ubasawa
  • Patent number: RE37979
    Abstract: The disclosure concerns pyrimidine derivatives represented by the following general formulas [I] and [I′] and having antiviral activity, particularly antiretroviral activity such as anti-HIV activity: and pharmaceutical compositions having antiviral activity and comprising the above-described derivative(s) as an active ingredient.
    Type: Grant
    Filed: October 23, 1997
    Date of Patent: February 4, 2003
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Tadashi Miyasaka, Hiromichi Tanaka, Erik Desiré DeClercq, Masanori Baba, Richard Thomas Walker, Masaru Ubasawa