Patents by Inventor Tadashi Nishimura
Tadashi Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118170Abstract: A vibration monitoring device includes: a rotation sensor for outputting a rotation signal synchronized with rotation of a rotational shaft; an output device for outputting a filter command value corresponding to a rotation speed of the rotational shaft calculated from the rotation signal; and at least one filter for extracting, in response to input of the rotation signal and the filter command value, a signal in a passband set according to the filter command value from the rotation signal as a vibration signal from which vibration information of the rotational shaft can be obtained.Type: ApplicationFiled: February 15, 2022Publication date: April 11, 2024Applicant: Mitsubishi Heavy Industries Marine Machinery & Equipment Co., Ltd.Inventors: Tadashi Yoshida, Hidetaka Nishimura, Akifumi Tanaka, Shinji Ogawa, Isao Tomita, Tohru Suita, Ryoji Sasaki
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Patent number: 10850466Abstract: A dynamic balance device for a press machine includes a plurality of cam portions which transmit a vertical motion of a slide to a balance weight to move the balance weight in a reverse direction of the vertical motion of the slide. The cam portions are each movable in a direction substantially orthogonal to a moving direction of the slide, and each include a first inclined surface and a second inclined surface. The first inclined surface has an inclination angle corresponding to an inclination angle of an inclined surface formed on a member which is provided integrally with the slide and vertically moves with the slide. The second inclined surface has an inclination angle corresponding to an inclination angle of an inclined surface formed on the balance weight.Type: GrantFiled: June 13, 2016Date of Patent: December 1, 2020Assignee: AIDA ENGINEERING LTD.Inventors: Takao Ito, Tadashi Nishimura
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Publication number: 20200031081Abstract: A dynamic balance device for a press machine includes a plurality of cam portions which transmit a vertical motion of a slide to a balance weight to move the balance weight in a reverse direction of the vertical motion of the slide. The cam portions are each movable in a direction substantially orthogonal to a moving direction of the slide, and each include a first inclined surface and a second inclined surface. The first inclined surface has an inclination angle corresponding to an inclination angle of an inclined surface formed on a member which is provided integrally with the slide and vertically moves with the slide. The second inclined surface has an inclination angle corresponding to an inclination angle of an inclined surface formed on the balance weight.Type: ApplicationFiled: June 13, 2016Publication date: January 30, 2020Applicants: AIDA ENGINEERING, LTD., AIDA ENGINEERING, LTD.Inventors: Takao ITO, Tadashi NISHIMURA
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Patent number: 10093075Abstract: A method for manufacturing a structure in which an edge portion of the structure formed by stacking a plurality of members is friction stir welded. The manufacturing method includes: a welding step of forming a friction stir welded portion by bringing a friction stir welding tool from a side of a surface of a member on one side into contact with a superposition portion of works in which the members are stacked while rotating the friction stir welding tool; and a cutting step of cutting the friction stir welded portion, and in each of two or more works produced by the cutting, a welded portion of the edge portion of the structure is formed with the cut friction stir welded portion.Type: GrantFiled: December 28, 2015Date of Patent: October 9, 2018Assignee: ISEL CO., LTD.Inventors: Noboru Mochizuki, Tadashi Nishimura
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Publication number: 20160129670Abstract: A method for manufacturing a structure in which an edge portion of the structure formed by stacking a plurality of members is friction stir welded. The manufacturing method includes: a welding step of foaming a friction stir welded portion by bringing a friction stir welding tool from a side of a surface of a member on one side into contact with a superposition portion of works in which the members are stacked while rotating the friction stir welding tool; and a cutting step of cutting the friction stir welded portion, and in each of two or more works produced by the cutting, a welded portion of the edge portion of the structure is formed with the cut friction stir welded portion.Type: ApplicationFiled: December 28, 2015Publication date: May 12, 2016Inventors: Noboru MOCHIZUKI, Tadashi NISHIMURA
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Patent number: 9084305Abstract: A lighting system includes a lighting load and a lighting control device. The lighting control device is configured to adjust a light output of the lighting load to a first light output corresponding to a first correlated color temperature and a first illuminance in a first time slot, and to decrease the light output of the lighting load up to a second light output corresponding to a second correlated color temperature and a second illuminance with the passage of time in a second time slot after the first time slot.Type: GrantFiled: February 6, 2013Date of Patent: July 14, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naohiro Toda, Hiroki Noguchi, Tadashi Nishimura, Shinsuke Nishioka, Toshikazu Kawashima
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Publication number: 20130229113Abstract: A lighting system includes a lighting load and a lighting control device. The lighting control device is configured to adjust a light output of the lighting load to a first light output corresponding to a first correlated color temperature and a first illuminance in a first time slot, and to decrease the light output of the lighting load up to a second light output corresponding to a second correlated color temperature and a second illuminance with the passage of time in a second time slot after the first time slot.Type: ApplicationFiled: February 6, 2013Publication date: September 5, 2013Applicant: PANASONIC CORPORATIONInventors: Naohiro TODA, Hiroki NOGUCHI, Tadashi NISHIMURA, Shinsuke NISHIOKA, Toshikazu KAWASHIMA
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Patent number: 8118347Abstract: An aspect in accordance with the present invention is a structure of mounting an impact absorption material for use with a vehicle. The structure includes: a door trim 30, a holder, and an EA pad. The holder includes a base and a plurality of legs, the base of the holder being disposed on the compartment outer side surface of the EA pad. The plurality of legs are disposed at intervals around an outer peripheral edge of the base of the holder and extend from the base of the holder, along an outer peripheral side surface of the EA pad, and to the door trim, thereby fixing the base of the holder to the door trim.Type: GrantFiled: June 2, 2010Date of Patent: February 21, 2012Assignees: Toyota Boshoku Kabushiki Kaisha, Hayashi Telempu Co., Ltd.Inventors: Akihiro Kawashima, Masami Uratsu, Michinori Kawasumi, Eiji Fujii, Tomonari Masuda, Tadashi Nishimura, Mariko Wada, Mamoru Yamaguchi, Kenichi Uemori
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Publication number: 20100308621Abstract: An aspect in accordance with the present invention is a structure of mounting an impact absorption material for use with a vehicle. The structure includes: a door trim 30, a holder, and an EA pad. The holder includes a base and a plurality of legs, the base of the holder being disposed on the compartment outer side surface of the EA pad. The plurality of legs are disposed at intervals around an outer peripheral edge of the base of the holder and extend from the base of the holder, along an outer peripheral side surface of the EA pad, and to the door trim, thereby fixing the base of the holder to the door trim.Type: ApplicationFiled: June 2, 2010Publication date: December 9, 2010Applicants: TOYOTA BOSHOKU KABUSHIKI KAISHA, HAYASHI TELEMPU CO., LTD.Inventors: Akihiro Kawashima, Masami Uratsu, Michinori Kawasumi, Eiji Fujii, Tomonari Masuda, Tadashi Nishimura, Mariko Wada, Mamoru Yamaguchi, Kenichi Uemori
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Publication number: 20040135211Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: ApplicationFiled: December 24, 2003Publication date: July 15, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Patent number: 6727552Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: GrantFiled: February 5, 2002Date of Patent: April 27, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Patent number: 6649976Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.Type: GrantFiled: October 22, 2001Date of Patent: November 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 6459125Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).Type: GrantFiled: July 27, 1998Date of Patent: October 1, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigenobu Maeda, Tadashi Nishimura, Kazuhito Tsutsumi, Shigeto Maegawa, Yuuichi Hirano
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Publication number: 20020110954Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).Type: ApplicationFiled: April 16, 2002Publication date: August 15, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigenobu Maeda, Tadashi Nishimura, Kazuhito Tsutsumi, Shigeto Maegawa, Yuuichi Hirano
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Publication number: 20020105031Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: ApplicationFiled: February 5, 2002Publication date: August 8, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Publication number: 20020048919Abstract: A semiconductor device in which parasitic resistance of source/drain regions can be reduced than the parasitic resistance of the drain region, and manufacturing method thereof, can be obtained. In the semiconductor device, inactivating ions are implanted only to the source region of the semiconductor layer, so as to damage the crystal near the surface of the semiconductor layer, whereby siliciding reaction is promoted. Therefore, in the source region, a titanium silicide film which is thicker can be formed.Type: ApplicationFiled: October 22, 2001Publication date: April 25, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Toshiaki Iwamatsu, Yasuo Inoue, Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 6358783Abstract: A semiconductor device includes a MOS-type field effect transistor (SOI-MOSFET) formed on a thin silicon layer on an insulator layer. The SOI-MOSFET has a gate overlap-type LDD structure in which additional source/drain regions having an impurity concentration of 3×1017 to 3×1018/cm3 overlapping with a gate electrode are provided in the silicon layer. According to this structure, when the SOI-MOSFET is on operation, only the additional source/drain regions are depleted, so that it is possible to obtain satisfactory transistor characteristics. Additional source/drain regions in this structure are formed by combination of vertical ion implantation using the gate electrode as a mask and thermal diffusion or oblique ion implantation using the gate electrode as a mask.Type: GrantFiled: January 20, 1999Date of Patent: March 19, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Yamaguchi, Tadashi Nishimura
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Patent number: 6351014Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: GrantFiled: March 6, 2000Date of Patent: February 26, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Publication number: 20020005552Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.Type: ApplicationFiled: March 6, 2000Publication date: January 17, 2002Inventors: Yasuo Inoue, Tadashi Nishimura, Yasuo Yamaguchi, Toshiaki Iwamatsu
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Publication number: 20020003259Abstract: A semiconductor device for CSP mounting which avoids errors due to alpha rays and is highly stress-resistant is provided. A buried oxide film (107) is formed on a semiconductor substrate (101), and a MOS transistor having an SOI structure is formed on the buried oxide film (107). The MOS transistor comprises source and drain regions (120a, 120b) formed in a semiconductor layer (120), and a gate electrode (110). An aluminum pad (103) connected to any one of the source and drain regions (120a, 120b) through a connecting mechanism not shown, and a silicon nitride film (104) having an opening on the top of the aluminum pad (103) are formed on an interlayer insulation film (108). A layer of titanium (105) and a layer of nickel (106) are formed extending from the aluminum pad (103) to an end of the silicon nitride film (104). A solder bump (11) is disposed on the layer of nickel (106).Type: ApplicationFiled: July 27, 1998Publication date: January 10, 2002Inventors: SHIGENOBU MAEDA, TADASHI NISHIMURA, KAZUHITO TSUTSUMI, SHIGETO MAEGAWA, YUUICHI HIRANO