Patents by Inventor Tadashi Ohshida

Tadashi Ohshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11843383
    Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: December 12, 2023
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Ching-Chao Huang, Jeremy Buan, Jingqian Tian, Tadashi Ohshida
  • Patent number: 11609478
    Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: March 21, 2023
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Kihong Kim, Jeremy Buan, Tsutomu Matsuo, Tadashi Ohshida
  • Patent number: 11585981
    Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: February 21, 2023
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Kihong Kim, Jeremy Buan, Tadashi Ohshida, Tsutomu Matsuo, Shuji Suzuki, Nobuhiro Tamai, Hiromichi Muraoka
  • Patent number: 11581883
    Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: February 14, 2023
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Ching-Chao Huang, Jeremy Buan, Jingqian Tian, Tadashi Ohshida
  • Publication number: 20220200587
    Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.
    Type: Application
    Filed: March 10, 2022
    Publication date: June 23, 2022
    Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
  • Publication number: 20220038083
    Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.
    Type: Application
    Filed: June 25, 2021
    Publication date: February 3, 2022
    Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
  • Publication number: 20210389642
    Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 16, 2021
    Inventors: Kihong KIM, Jeremy BUAN, Tsutomu MATSUO, Tadashi OHSHIDA
  • Publication number: 20210325608
    Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.
    Type: Application
    Filed: March 29, 2021
    Publication date: October 21, 2021
    Inventors: Kihong KIM, Jeremy BUAN, Tadashi OHSHIDA, Tsutomu MATSUO, Shuji SUZUKI, Nobuhiro TAMAI, Hiromichi MURAOKA
  • Patent number: 10756465
    Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: August 25, 2020
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Nobuhiro Tamai, Shota Yamada, Clement Kam Lam Luk, Jeremy Buan, Ching-Chao Huang, Tadashi Ohshida
  • Patent number: 10249989
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: April 2, 2019
    Assignee: HIROSE ELECTRIC CO., LTD.
    Inventors: Clement Luk, Jeremy Buan, Tadashi Ohshida, Ching-Chao Huang
  • Publication number: 20180261961
    Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.
    Type: Application
    Filed: January 24, 2018
    Publication date: September 13, 2018
    Inventors: Clement LUK, Jeremy BUAN, Tadashi OHSHIDA, Ching-Chao HUANG
  • Patent number: 7976316
    Abstract: An electrical connector for connecting a circuit board includes a plurality of blades; a plurality of terminals disposed on each of the blades and extending in parallel to each other; and a holding member for holding the blades next to each other to be situated on a same plane. Further, each of the blades includes a base member, and the terminals are integrated with the base member.
    Type: Grant
    Filed: September 10, 2009
    Date of Patent: July 12, 2011
    Assignee: Hirose Electric Co., Ltd.
    Inventor: Tadashi Ohshida
  • Publication number: 20100075538
    Abstract: An electrical connector for connecting a circuit board includes a plurality of blades; a plurality of terminals disposed on each of the blades and extending in parallel to each other; and a holding member for holding the blades next to each other to be situated on a same plane. Further, each of the blades includes a base member, and the terminals are integrated with the base member.
    Type: Application
    Filed: September 10, 2009
    Publication date: March 25, 2010
    Inventor: Tadashi OHSHIDA
  • Patent number: 7604483
    Abstract: An electrical connector assembly has a fixed connector, a middle connector, and a plug connector. The fixed connector is attached to a circuit member of an electrical device. The middle connector is connected and pulled out to and from the fixed connector in a direction same as that of the plug connector being connected and pulled out to and from the middle connector. Each of the fixed connector, the middle connector, and the plug connector is provided with engagement portions at both end portions thereof in a direction parallel to a straight line extending in a different direction from an insertion and pull-out direction. With the engagement portions, it is possible to prevent the fixed connector from coming off from the middle connector when the plug connector is pulled out.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: October 20, 2009
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Toshiyuki Takada, Tadashi Ohshida
  • Publication number: 20080242161
    Abstract: An electrical connector assembly has a fixed connector, a middle connector, and a plug connector. The fixed connector is attached to a circuit member of an electrical device. The middle connector is connected and pulled out to and from the fixed connector in a direction same as that of the plug connector being connected and pulled out to and from the middle connector. Each of the fixed connector, the middle connector, and the plug connector is provided with engagement portions at both end portions thereof in a direction parallel to a straight line extending in a different direction from an insertion and pull-out direction. With the engagement portions, it is possible to prevent the fixed connector from coming off from the middle connector when the plug connector is pulled out.
    Type: Application
    Filed: December 20, 2007
    Publication date: October 2, 2008
    Inventors: Toshiyuki Takada, Tadashi Ohshida
  • Patent number: 7413475
    Abstract: An electrical connector (10) has ground planes (13). Each ground plane (13) crosses counter ground planes (36) of the counter connector (30) so as to make a lattice structure when the counter connector (30) is fitted to the connector (10). The contact section (12C) of a signal terminal (12) of the connector (10) has a plane surface perpendicular to the surface of the corresponding counter contact section (34A) of the counter signal terminal (34), and formed at a flexible elastic arm (12B) in the plane surface. The ground plane (13) has pressure-welding sections (18B) and (20B), which individually elastically contact with the facing inner surfaces of each slit, at a portion to be put into each slit of the counter ground plane (36).
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: August 19, 2008
    Assignee: Hirose Electric Co., Ltd.
    Inventors: Tsutomu Matsuo, Tadashi Ohshida
  • Publication number: 20070066140
    Abstract: An electrical connector (10) has ground planes (13). Each ground plane (13) crosses counter ground planes (36) of the counter connector (30) so as to make a lattice structure when the counter connector (30) is fitted to the connector (10). The contact section (12C) of a signal terminal (12) of the connector (10) has a plane surface perpendicular to the surface of the corresponding counter contact section (34A) of the counter signal terminal (34), and formed at a flexible elastic arm (12B) in the plane surface. The ground plane (13) has pressure-welding sections (18B) and (20B), which individually elastically contact with the facing inner surfaces of each slit, at a portion to be put into each slit of the counter ground plane (36).
    Type: Application
    Filed: September 14, 2006
    Publication date: March 22, 2007
    Inventors: Tsutomu Matsuo, Tadashi Ohshida