Patents by Inventor Tadashi Ohshida
Tadashi Ohshida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11843383Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.Type: GrantFiled: June 25, 2021Date of Patent: December 12, 2023Assignee: Hirose Electric Co., Ltd.Inventors: Ching-Chao Huang, Jeremy Buan, Jingqian Tian, Tadashi Ohshida
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Patent number: 11609478Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.Type: GrantFiled: May 26, 2021Date of Patent: March 21, 2023Assignee: Hirose Electric Co., Ltd.Inventors: Kihong Kim, Jeremy Buan, Tsutomu Matsuo, Tadashi Ohshida
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Patent number: 11585981Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.Type: GrantFiled: March 29, 2021Date of Patent: February 21, 2023Assignee: Hirose Electric Co., Ltd.Inventors: Kihong Kim, Jeremy Buan, Tadashi Ohshida, Tsutomu Matsuo, Shuji Suzuki, Nobuhiro Tamai, Hiromichi Muraoka
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Patent number: 11581883Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.Type: GrantFiled: March 10, 2022Date of Patent: February 14, 2023Assignee: Hirose Electric Co., Ltd.Inventors: Ching-Chao Huang, Jeremy Buan, Jingqian Tian, Tadashi Ohshida
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Publication number: 20220200587Abstract: A method of manufacturing an electrical system for reducing differential-to-differential far end crosstalk (DDFEXT) includes converting a first S parameter representative of a design of a first electrical system into a differential-only S parameter, generating a second differential-only S parameter configured to add even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter of the electrical system such that a total even-mode propagation delay and odd-mode propagation delay of the differential-only S parameter are substantially equivalent, and reconfiguring a second electrical system from the differential-only S parameter and the second differential-only S parameter.Type: ApplicationFiled: March 10, 2022Publication date: June 23, 2022Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
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Publication number: 20220038083Abstract: Example implementations described herein are directed to reducing far end cross talk (FEXT), including differential-to-differential far end crosstalk (DDFEXT) or single ended FEXT through generating and applying a delay shifter/inverter that is cascaded onto a target electrical system and shifts the even-mode and odd-mode propagation delay of a target electrical system to be substantially equal, which in turn reduces FEXT in the overall system.Type: ApplicationFiled: June 25, 2021Publication date: February 3, 2022Inventors: Ching-Chao HUANG, Jeremy BUAN, Jingqian TIAN, Tadashi OHSHIDA
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Publication number: 20210389642Abstract: Example implementations described herein are directed to an interface configured to redirect light between a connector connected to a printed optical board (POB) via an optical waveguide, and a photonic integrated circuit (PIC), the interface involving two-dimensionally distributed waveplates (TDWs) having multiple layers of p-doped and n-doped silicon, the TDWs configured to be driven to change a dielectric constant at a two dimensional location on the TDWs such that the received light is redirected at the two dimensional location.Type: ApplicationFiled: May 26, 2021Publication date: December 16, 2021Inventors: Kihong KIM, Jeremy BUAN, Tsutomu MATSUO, Tadashi OHSHIDA
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Publication number: 20210325608Abstract: Example implementations described herein are directed to a system involving one or more photonic integrated circuits having multi-mode waveguides and connected to a printed optical board through the use of multi-mode waveguide connectors described herein. The printed optical board can include an embedded multi-mode waveguide bus to facilitate optical signal to and from the photonic integrated circuits. The system can also include a chiplet such as a photonic integrated circuit with a single mode waveguide configured to connect to an optical fiber cable.Type: ApplicationFiled: March 29, 2021Publication date: October 21, 2021Inventors: Kihong KIM, Jeremy BUAN, Tadashi OHSHIDA, Tsutomu MATSUO, Shuji SUZUKI, Nobuhiro TAMAI, Hiromichi MURAOKA
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Patent number: 10756465Abstract: The first terminals have contact arm portions extending in a rectilinear manner in the direction of connector plugging and unplugging; the second terminals have convex contact point portions contactable with an intermediate portion of the contact arm portions in the same direction. When the stub portions of the contact arm portions are divided into a free end side range and a proximal end side range such that the center point of said stub portions in the direction of plugging and unplugging forms a boundary, in the arranged state of the first terminals, impedance at arbitrary locations in the direction of plugging and unplugging within the free end side range is larger than impedance at arbitrary locations in the plugging direction within the proximal end side range.Type: GrantFiled: September 6, 2019Date of Patent: August 25, 2020Assignee: HIROSE ELECTRIC CO., LTD.Inventors: Nobuhiro Tamai, Shota Yamada, Clement Kam Lam Luk, Jeremy Buan, Ching-Chao Huang, Tadashi Ohshida
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Patent number: 10249989Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.Type: GrantFiled: January 24, 2018Date of Patent: April 2, 2019Assignee: HIROSE ELECTRIC CO., LTD.Inventors: Clement Luk, Jeremy Buan, Tadashi Ohshida, Ching-Chao Huang
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Publication number: 20180261961Abstract: Example implementations described herein are directed to a method and apparatus for improving insertion loss of connector stub and thereby increasing a system's signal bandwidth. This technique shapes the connector stub in a specific way to shift its resonant frequency higher while having equal or better electrical performance below the original resonant frequency.Type: ApplicationFiled: January 24, 2018Publication date: September 13, 2018Inventors: Clement LUK, Jeremy BUAN, Tadashi OHSHIDA, Ching-Chao HUANG
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Patent number: 7976316Abstract: An electrical connector for connecting a circuit board includes a plurality of blades; a plurality of terminals disposed on each of the blades and extending in parallel to each other; and a holding member for holding the blades next to each other to be situated on a same plane. Further, each of the blades includes a base member, and the terminals are integrated with the base member.Type: GrantFiled: September 10, 2009Date of Patent: July 12, 2011Assignee: Hirose Electric Co., Ltd.Inventor: Tadashi Ohshida
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Publication number: 20100075538Abstract: An electrical connector for connecting a circuit board includes a plurality of blades; a plurality of terminals disposed on each of the blades and extending in parallel to each other; and a holding member for holding the blades next to each other to be situated on a same plane. Further, each of the blades includes a base member, and the terminals are integrated with the base member.Type: ApplicationFiled: September 10, 2009Publication date: March 25, 2010Inventor: Tadashi OHSHIDA
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Patent number: 7604483Abstract: An electrical connector assembly has a fixed connector, a middle connector, and a plug connector. The fixed connector is attached to a circuit member of an electrical device. The middle connector is connected and pulled out to and from the fixed connector in a direction same as that of the plug connector being connected and pulled out to and from the middle connector. Each of the fixed connector, the middle connector, and the plug connector is provided with engagement portions at both end portions thereof in a direction parallel to a straight line extending in a different direction from an insertion and pull-out direction. With the engagement portions, it is possible to prevent the fixed connector from coming off from the middle connector when the plug connector is pulled out.Type: GrantFiled: December 20, 2007Date of Patent: October 20, 2009Assignee: Hirose Electric Co., Ltd.Inventors: Toshiyuki Takada, Tadashi Ohshida
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Publication number: 20080242161Abstract: An electrical connector assembly has a fixed connector, a middle connector, and a plug connector. The fixed connector is attached to a circuit member of an electrical device. The middle connector is connected and pulled out to and from the fixed connector in a direction same as that of the plug connector being connected and pulled out to and from the middle connector. Each of the fixed connector, the middle connector, and the plug connector is provided with engagement portions at both end portions thereof in a direction parallel to a straight line extending in a different direction from an insertion and pull-out direction. With the engagement portions, it is possible to prevent the fixed connector from coming off from the middle connector when the plug connector is pulled out.Type: ApplicationFiled: December 20, 2007Publication date: October 2, 2008Inventors: Toshiyuki Takada, Tadashi Ohshida
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Patent number: 7413475Abstract: An electrical connector (10) has ground planes (13). Each ground plane (13) crosses counter ground planes (36) of the counter connector (30) so as to make a lattice structure when the counter connector (30) is fitted to the connector (10). The contact section (12C) of a signal terminal (12) of the connector (10) has a plane surface perpendicular to the surface of the corresponding counter contact section (34A) of the counter signal terminal (34), and formed at a flexible elastic arm (12B) in the plane surface. The ground plane (13) has pressure-welding sections (18B) and (20B), which individually elastically contact with the facing inner surfaces of each slit, at a portion to be put into each slit of the counter ground plane (36).Type: GrantFiled: September 14, 2006Date of Patent: August 19, 2008Assignee: Hirose Electric Co., Ltd.Inventors: Tsutomu Matsuo, Tadashi Ohshida
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Publication number: 20070066140Abstract: An electrical connector (10) has ground planes (13). Each ground plane (13) crosses counter ground planes (36) of the counter connector (30) so as to make a lattice structure when the counter connector (30) is fitted to the connector (10). The contact section (12C) of a signal terminal (12) of the connector (10) has a plane surface perpendicular to the surface of the corresponding counter contact section (34A) of the counter signal terminal (34), and formed at a flexible elastic arm (12B) in the plane surface. The ground plane (13) has pressure-welding sections (18B) and (20B), which individually elastically contact with the facing inner surfaces of each slit, at a portion to be put into each slit of the counter ground plane (36).Type: ApplicationFiled: September 14, 2006Publication date: March 22, 2007Inventors: Tsutomu Matsuo, Tadashi Ohshida