Abstract: Provided is a curcumin pharmaceutical preparation that is highly water soluble, can maintain the concentration of free curcumin in the blood sufficiently high by being administered parenterally, can effectively obtain a pharmacological action of curcumin, and is highly safe. A pharmaceutical composition for parenteral administration, including a water-soluble substance conjugate of curcumin as an active component.

Abstract: A three-dimensional map generation system (500) generates three-dimensional map information (11) by using measured data acquired by a measurement vehicle (200) moving in a measurement area (50). A determination unit (120) determines, from the measurement area (50), a data shortage area where measured data for generating the three-dimensional map falls short, based on first measured data (20) transmitted from the measurement vehicle (200). A generation unit (130) generates interpolated data which interpolates three-dimensional map information of a defective area with a NURBS curve so that a lateral G, which is centrifugal force in a lateral direction applied to a traveling vehicle traveling a road in the defective area at a traveling speed, is equal to or less than a predefined threshold (12).

Abstract: A three-dimensional map generation system (500) generates three-dimensional map information (11) by using measured data acquired by a measurement vehicle (200) moving in a measurement area (50). A determination unit (120) determines, from the measurement area (50), a data shortage area where measured data for generating the three-dimensional map falls short, based on first measured data (20) transmitted from the measurement vehicle (200). A generation unit (130) generates interpolated data which interpolates three-dimensional map information of a defective area with a NURBS curve so that a lateral G, which is centrifugal force in a lateral direction applied to a traveling vehicle traveling a road in the defective area at a traveling speed, is equal to or less than a predefined threshold (12).

Abstract: In an ESD protection circuit, the overvoltage detection circuit detects application of an overvoltage to a power supply node. A clamp circuit connects the power supply node to a ground node to clamp a voltage of the power supply node. A voltage regulation circuit drops the voltage of the power supply node to generate a predetermined regulated voltage to be supplied to the overvoltage detection circuit as a power supply voltage. At the predetermined regulated voltage, the overvoltage detection circuit is not activated at Power-On, and is activated under ESD events. A voltage compensation circuit compensates for the voltage of the detection signal, so that the voltage of the detection signal becomes equal to the overvoltage, when the overvoltage is applied to the power supply node.

Abstract: A luminescent nanosheet has perovskite octahedral crystal units combined together in a planar configuration. The octahedral crystal units each have a multistacked crystal sheet structure. The octahedral crystal units are multistacked over at least 3 high in a direction vertical to a sheet plane, and an element providing a luminescence center is solid-solubilized between the multistacked octahedral crystal units.

Abstract: In an ESD protection circuit, the overvoltage detection circuit detects application of an overvoltage to a power supply node. A clamp circuit connects the power supply node to a ground node to clamp a voltage of the power supply node. A voltage regulation circuit drops the voltage of the power supply node to generate a predetermined regulated voltage to be supplied to the overvoltage detection circuit as a power supply voltage. At the predetermined regulated voltage, the overvoltage detection circuit is not activated at Power-On, and is activated under ESD events. A voltage compensation circuit compensates for the voltage of the detection signal, so that the voltage of the detection signal becomes equal to the overvoltage, when the overvoltage is applied to the power supply node.

Abstract: A luminescent nanosheet has perovskite octahedral crystal units combined together in a planar configuration. The octahedral crystal units each have a multistacked crystal sheet structure. The octahedral crystal units are multistacked over at least 3 high in a direction vertical to a sheet plane, and an element providing a luminescence center is solid-solubilized between the multistacked octahedral crystal units.

Abstract: A luminescent nanosheet has perovskite octahedral crystals combined together in a planar configuration, and the octahedral crystals each have a multistacked crystal sheet structure wherein the octahedral crystals are multistacked over at least 3 folds in the direction vertical to a sheet plane, and an element providing a luminescence center is solid-solubilized between the multistacked octahedral crystals.

Abstract: The invention provides a novel luminescent nanosheet, and applications to that luminescent nanosheet. The invention also breaks down conventional common knowledge of nanosheet solutions to provide a nanosheet paint that makes use of a high-concentration nanosheet solution suitable for dispersion of a luminescent nanosheet or the like. The invention provides a luminescent nanosheet having perovskite octahedral crystals combined together in a planar configuration, characterized in that the octahedral crystals each have a multistacked crystal sheet structure wherein the octahedral crystals are multistacked over at least 3 high in the direction vertical to a sheet plane, and an element providing a luminescence center is solid-solubilized between the multistacked octahedral crystals (see FIG. 8).

Abstract: A master-slave circuit that includes a master circuit having input data stored therein, a storage unit for receiving the input data in response to receiving a sleep mode setting signal that sets a sleep mode, and for storing the input data, and a first control unit for interrupting the supply of a power supply voltage to the master circuit after the input data is stored in the storage unit.

Abstract: A semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to change and addition of test specifications without having to perform complicated control with a complicated and large-scale circuit structure is provided. As memory operation specification information, capacity information R1, bus width information R2, and burst length information R3 are inputted from the outside and stored in a capacity information storing circuit 1, a bus-width-information storing circuit 2, and a burst-length-information storing circuit 3. The stored information R1 to R3 is inputted to a max./min. value generator circuit 11, and a maximum address AMAX1 and a minimum address AMIN1 are generated at the max./min. value generator circuit 11. Since the memory operation specification information such as the information R1 to R3 is rewritten from the outside, the maximum address AMAX1 and the minimum address AMIN1 in an address space can be set in accordance with the specifications.

Abstract: A semiconductor memory device having a self-diagnostic test function which enables flexible adjustment to change and addition of test specifications without having to perform complicated control with a complicated and large-scale circuit structure is provided. As memory operation specification information, capacity information R1, bus width information R2, and burst length information R3 are inputted from the outside and stored in a capacity information storing circuit 1, a bus-width-information storing circuit 2, and a burst-length-information storing circuit 3. The stored information R1 to R3 is inputted to a max./min. value generator circuit 11, and a maximum address AMAX1 and a minimum address AMIN1 are generated at the max./min. value generator circuit 11. Since the memory operation specification information such as the information R1 to R3 is rewritten from the outside, the maximum address AMAX1 and the minimum address AMIN1 in an address space can be set in accordance with the specifications.

Abstract: A thermal resistance variable heat sink structure is provided that can improve the quality during operation and that can change the shape of a heat sink and reduce the number of steps attaching and detaching. Solder balls 1 are disposed for connection of a LSI 2. A mounting plate 3 on which a heat sink is mounted, screws 4 for mounting the heat sink, a radiation fin 5, and a thermal resistance adjuster 6 are disposed on the back surface of the LSI 2. The thermal resistance adjuster 6 is placed on the middle of the back surface to cut the cooling air.

Abstract: In a failure analysis method for a ball grid array type semiconductor device including a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.

Abstract: In a failure analysis method for a ball grid array type semiconductor device comprising a semiconductor chip having pads, first solder balls, an interposer substrate and second solder balls, the second solder balls and the interposer substrate are removed from the semiconductor device, and then, the first solder balls are removed from the semiconductor device. Then, the semiconductor device is mounted on a package, and a wire bonding operation is performed between the pads of the semiconductor chip and bonding pads of the package. Finally, a test operation is performed upon the semiconductor chip by mounting the package on a tester.

Abstract: A thermal resistance variable heat sink structure is provided that can improve the quality during operation and that can change the shape of a heat sink and reduce the number of steps attaching and detaching. Solder balls 1 are disposed for connection of a LSI 2. A mounting plate 3 on which a heat sink is mounted, screws 4 for mounting the heat sink, a radiation fin 5, and a thermal resistance adjuster 6 are disposed on the back surface of the LSI 2. The thermal resistance adjuster 6 is placed on the middle of the back surface to cut the cooling air.

Abstract: A binded carbon brush includes a brush main portion formed mainly of carbon, and an electric conductor formed by a material, such as a copper powder, having an electric resistivity lower than that of the brush main portion and extending along a main current direction of the brush. In the cross section of the brush perpendicular to the main current direction, the diameter or the vertical and horizontal sizes of the conductor is so set as to be smaller than both the vertical and horizontal sizes of the brush main portion.

Abstract: Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source.

Abstract: A binded carbon brush includes a brush main portion formed mainly of carbon, and an electric conductor formed by a material, such as a copper powder, having an electric resistivity lower than that of the brush main portion and extending along a main current direction of the brush. In the cross section of the brush perpendicular to the main current direction, the diameter or the vertical and horizontal sizes of the conductor is so set as to be smaller than both the vertical and horizontal sizes of the brush main portion.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type; an epitaxial layer of a second conductivity type formed on the semiconductor substrate; an impurity diffusion layer of the second conductivity type embedded between the semiconductor substrate and the epitaxial layer and having an impurity concentration greater than that of the epitaxial layer; a resistance region reaching the impurity diffusion layer from a surface of the epitaxial layer and extending substantially vertically to the surface of the epitaxial layer; an insulating film defining the resistance region; and a lead region selectively formed between the surface of the epitaxial layer and the impurity diffusion layer.