Patents by Inventor Tadashi Tanimoto
Tadashi Tanimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7707523Abstract: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.Type: GrantFiled: September 19, 2006Date of Patent: April 27, 2010Assignee: Panasonic CorporationInventors: Kiyohito Mukai, Tadashi Tanimoto, Mitsumi Ito
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Patent number: 7337423Abstract: Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.Type: GrantFiled: February 17, 2004Date of Patent: February 26, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami
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Publication number: 20070174807Abstract: To provide a semiconductor device manufacturing method of making a pattern formation possible with high precision at a high speed, the same block can be completed by one process a cell by dividing the layout data into cells in the OPC processing step and then applying the OPC to each cell, and the OPC is applied only to the cell boundary portions after respective OPC-applied cells are arranged on the chip, so that a dimensional precision in vicinity of the cell boundaries can be ensured. Also, since the patterns on the cell boundary portions are caused to shrink uniformly, the OPC of the cell boundary portions can be simplified and thus the fast process can be applied.Type: ApplicationFiled: July 18, 2006Publication date: July 26, 2007Inventors: Masahiko Kumashiro, Tadashi Tanimoto
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Publication number: 20070051995Abstract: A MOS transistor cell having a salicide structure has a plurality of gate wires each formed as a straight line with a constant width. Each of the gate wires includes a P-channel gate terminal and an N-channel gate terminal. The P-side ends and the N-side ends of the gate wires are connected by means of respective two gate wire connecting portions at a boundary portion between the MOS transistor cell and another adjacent MOS transistor cell.Type: ApplicationFiled: September 7, 2006Publication date: March 8, 2007Inventors: Masahiko Kumashiro, Tadashi Tanimoto
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Publication number: 20070020880Abstract: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.Type: ApplicationFiled: September 19, 2006Publication date: January 25, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyohito Mukai, Tadashi Tanimoto, Mitsumi Ito
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Publication number: 20070009147Abstract: A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.Type: ApplicationFiled: September 11, 2006Publication date: January 11, 2007Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Hiroyuki Tsujikawa, Tadashi Tanimoto
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Patent number: 7115478Abstract: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.Type: GrantFiled: September 17, 2003Date of Patent: October 3, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kiyohito Mukai, Tadashi Tanimoto, Mitsumi Ito
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Patent number: 7114144Abstract: A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.Type: GrantFiled: November 26, 2003Date of Patent: September 26, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shinya Tokunaga, Hiroyuki Tsujikawa, Tadashi Tanimoto
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Publication number: 20040243967Abstract: Reduction in labor of the operations for evaluating the amount of retrogression of end portions in a line pattern, and the simplification of the CAD processing for a mask are achieved. A semiconductor design layout pattern formation method is provided concerning a layout pattern on a wafer, wherein the designed wire lines do not have the same pitch, and wherein a dummy graphic pattern having no relation to wiring is formed in a non-wired region of the layout pattern so that the interval between the dummy graphic pattern and the adjacent wiring line becomes equal to the intervals of wiring lines. It becomes possible to make uniform the pitch of the end portions of lines in the design layout pattern on the wafer, so that the dispersion in the change of the form (retrogression) of the end portions of the lines can be restricted.Type: ApplicationFiled: May 24, 2004Publication date: December 2, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami
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Publication number: 20040191644Abstract: Established is a mask pattern correcting technique for reducing the load to a mask CAD process and for ensuring the minimum dimension defined in an OPC process. A method comprises the steps of: measuring a line width of a mask pattern; extracting edges where the line width of the mask pattern is smaller than a predetermined dimension; generating a central geometrical object having a predetermined width relative to the center between the edges where the line width is smaller than the predetermined dimension; and replacing the portion of the mask pattern where the line width is smaller than the predetermined dimension with the central geometrical object. As a result, the mask pattern line width is changed into the predetermined with dimension of the central geometrical object. This reduces notably the number of geometrical object calculating steps that had been performed for each value of dimension on the basis of a correction table in the prior art, and thereby shortens the mask CAD processing time.Type: ApplicationFiled: February 17, 2004Publication date: September 30, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Minoru Yamagiwa, Tadashi Tanimoto, Akio Misaka, Reiko Hinogami
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Publication number: 20040148584Abstract: A method of inspecting a photomask for a semiconductor integrated circuit formed based on drawing pattern data, includes the steps of classifying a drawing pattern of the semiconductor integrated circuit into a plurality of ranks in accordance with a predetermined reference and extracting the same, determining inspecting accuracy for each of the ranks, and deciding quality of the photomask depending on whether the determined inspecting accuracy is satisfied.Type: ApplicationFiled: November 26, 2003Publication date: July 29, 2004Inventors: Shinya Tokunaga, Hiroyuki Tsujikawa, Tadashi Tanimoto
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Publication number: 20040083445Abstract: At least a groove for separating a semiconductor substrate into a first region of a relatively large area and a second region of a relatively small area is formed. An insulating film is formed on the surface of the semiconductor substrate including the interior of the groove. The insulating film is etched using an etching mask having a lattice window pattern in such a manner that openings corresponding to the lattice window pattern are formed in the first region. As an alternative, openings corresponding to a single opening pattern are formed in the first region using an etching mask having the single opening pattern and the lattice window pattern, and the insulating film is etched in such a manner that openings corresponding to the lattice window pattern are formed in the second region. In both cases, the remaining insulating film is polished off.Type: ApplicationFiled: September 17, 2003Publication date: April 29, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Kiyohito Mukai, Tadashi Tanimoto, Mitsumi Ito
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Patent number: 5236885Abstract: Disclosed are a sheet for taking a print of an object, the sheet comprising (a) a substrate, and (b) a coating layer formed over the whole surface or part of the surface of the substrate and comprising a colorless or pale-colored basic dye, a color developing material which develops a color on contact with the dye and an adhesive, the whole of the coating layer being colored by the color-forming reaction of the basic dye and the color developing material; a method of taking a print of an object with use of the sheet comprising applying a desensitizer to the object and contacting the desensitizer with the sheet; and a kit for this purpose comprising the sheet and a desensitizer.Type: GrantFiled: November 27, 1991Date of Patent: August 17, 1993Assignee: Kanzaki Paper Manufacturing Co., Ltd.Inventor: Tadashi Tanimoto
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Patent number: 5130290Abstract: Disclosed are a water-sensitive coloring sheet comprising:(a) a substrate and(b) a water-sensitive coloring layer containing a colorless or pale-colored basic dye, a color developing material capable of forming a color on contact with the dye, a densensitizer and a binder, and a method for forming colored image on such water-sensitive coloring sheet by application of water.Type: GrantFiled: March 22, 1990Date of Patent: July 14, 1992Assignee: Kanzaki Paper Manufacturing Co., Ltd.Inventor: Tadashi Tanimoto
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Patent number: 3956562Abstract: An electrostatic recording material having excellent recording characteristics is obtained by coating an electrically conductive substrate with a coating composition comprising an insulating polymer and pigment particles on which is adsorbed a fatty acid having at least five carbon atoms, ester or salt thereof, or resin acid or salt thereof.Type: GrantFiled: March 5, 1974Date of Patent: May 11, 1976Assignee: Kanzaki Paper Manufacturing Co., Ltd.Inventors: Kazuo Shibata, Tadashi Tanimoto