Abstract: In a test mode, bit information of the same logic is written into a corresponding memory cell of each of subarray 5a-5d. Bit information written in respective memory cells is simultaneously read and supplied to exclusive-OR gates 12a-12d. Each of exclusive-OR gates logics of read bit information and an expected value data supplied as an input to an external input pin D.sub.IN to supply the test determination result as an output. The outputs of respective exclusive-OR gates 12a-12d are serially supplied, through transistors 18a-18d which are sequentially and selectively turned on by a shift register 15, to an external output pin D.sub.OUT.

Abstract: An input circuit of a semiconductor device includes a P type well formed on the main surface of a semiconductor substrate, and an N type region formed on the main surface in the P type well. A P-N junction is formed by the N type region and the P type well. An input voltage is applied to the N type region, which input voltage is applied to an internal circuit formed on the semiconductor substrate. When the P-N junction is rendered conductive by an application of an excessive voltage to the input voltage, the current caused by the excessive voltage is absorbed to the supply potential through the P type region formed in the P well.

Abstract: A method of manufacturing an input circuit of a semiconductor device comprises the steps of forming an N well on the main surface of a P type semiconductor substrate, forming a P well by injecting P type ions upwardly from the N well, and forming an N type region by injecting ions onto the main surface of the P well. An input voltage is applied to the N type region, and the input voltage is applied to the internal circuit formed on the main surface of the semiconductor substrate. A P-N junction is formed between the P well and an N type diffusion layer. When the P-N junction conducts due to the application of an excess voltage into the input voltage, current caused by the excess voltage is absorbed through the N type region formed on the main surface of the N well.

Abstract: A semiconductor integrated circuit device including a semiconductor substrate having a main surface; a first conductive region formed on the main surface; a second conductive region formed on the main surface, spaced apart from the first conductive region and to be electrically connected to the first conductive region; and a capacitor having a storage node connecting the first and second conductive regions. The storage node serves to connect the first and second conductive regions and simultaneously stores charges. In other aspects of the invention, there are provided a memory cell having a structure described above, and a method of manufacturing the above-described semiconductor integrated circuit device.

Abstract: A semiconductor memory device comprises a plurality or CAM cells. In a refreshing operation, data of "1" is applied to all of bit lines and inversion bit lines. In the CAM cells storing the data "1", writing of the data "1" onto the bit lines and the inversion bit lines is performed. Then, the data of "0" is applied to all of the bit lines and the inversion bit lines. In the CAM cells storing the data "0", writing of the data "0" onto the bit lines and the inversion bit lines is performed. In a partial writing operation, in the CAM cells to which writing is performed, a first control node is activated, thereby making it possible to write the CAM cells. In the rest of the CAM cells, the first control node is inactivated, thereby making it impossible to write the CAM cells.

Abstract: An integrated circuit having a superconductive wiring comprises a semiconductor substrate, an integrated circuit device formed on the semiconductor substrate and a wiring connected to the integrated circuit device. The wiring is formed of a superconductive material and has a wide portion for heat radiation. The manufacturing method of the same comprises the steps of preparing a semiconductor substrate, forming an integrated circuit device on the semiconductor substrate, and connecting a wiring having a wide portion for heat radiation and formed of a superconductive material to the integrated circuit device on the semiconductor substrate.

Abstract: A testing circuit for a semiconductor memory device is provided. An AND operation is performed on the data read out from each block of a memory cell array when the bit data written into each block of the memory cell array for testing is "1", and a NOR operation is performed on the data read out from each block of the memory cell array when the bit data written into each block of the memory cell array is "0". In this manner, even when the data read out from the blocks are all inverted in their logical states through error, such error can be detected.

Abstract: The present invention comprises a field oxide film formed on a silicon substrate, an underlying film of polycrystal silicon formed on a portion thereof and an insulating film formed so as to cover the field oxide film comprising the underlying film. A surface stepped portion of the insulating film is formed by a portion with an underlying film and a portion without an underlying film under the insulating film, and a blowout portion of a fuse is formed along the surface stepped portion. There are terminal portions at both ends of the blowout portion of the fuse and an aluminum line is connected thereto. In addition, the whole portions comprising the fuse portion are covered with another insulating film and the whole is protected. The fuse is employed as one example in a redundancy circuit of a MOS dynamic RAM having redundancy memory cells.

Abstract: A semiconductor device having a bonding pad arrangement adaptable both to a package specification which requires lead terminals only along one longitudinal side of the package and to a specification which requires lead terminals to be arranged on both longitudinal sides of the package.

Abstract: A substrate bias circuit controls application of a conventional substrate charge pump to the substrate of a semiconductor integrated circuit to prevent latching up of parasitic transistors at the time of turn on of power to the integrated circuit. The substrate bias circuit comprises a filed effect transistor having its source and drain electrodes connected between substrate and charge pump. The gate electrode of the transistor is driven through an RC circuit by the power supply to turn on the transistor for a predetermined time period at the time power is initially applied to the integrated circuit. There is no latching up of the parasitic transistors because application of positive bias voltage to the substrate during turn-on is prevented.

Abstract: The switching circuit 4 receives external address signals EXT. A.sub.0 to A.sub.8 or output signals Q.sub.0 to Q.sub.8 from the refresh counter 2 and selects either of these signals in response to the clock signals .phi..sub.2 and .phi..sub.2 to apply the same to the address buffer 1. A plurality of N type field effect transistors, which operate in response to the clock signal .phi..sub.3, such as transistors 540, 54 and 548 are connected between each of the inputs of the switching circuit 4 for receiving the external address signals EXT. A.sub.0 to A.sub.8 and the ground V.sub.ss. Referring to the i-th circuit portion, before the switching circuit 4 applies a signal Q.sub.i from the refresh counter 2 to the address buffer 1, the transistor 54 turns on in response to the clock signal .phi..sub.3 and brings the input of the address buffer 1 to the voltage level of the ground V.sub.ss. When the switching circuit 4 is switched, the signal from the refresh counter 2 is correctly applied to the address buffer 1.

Abstract: An internal power supply voltage generator for generating an internal power supply voltage for a semiconductor integrated device includes first and second reference voltage generators which produce first and second reference voltages having respective values a predetermined amount above and below an optimal value of the internal power supply voltage. The first and second reference voltage generators are constructed of a pair of serially connected NMOS and PMOS transistors, respectively, which transistors are connected between an external voltage supply and ground. The first and second reference voltages are applied to a CMOS output stage constructed of a NMOS and PMOS transistor serially connected between the external voltage supply and ground, the gates of the transistors being coupled to the first and second reference voltages, so as to provide said internal power supply voltage at a common node between the transistors.

Abstract: A dynamic random access memory comprises N channel sense amplifiers, P channel sense amplifiers and an equalizing MOSFET each provided for each of bit line pairs. The N channel sense amplifiers and the P channel sense amplifiers are operated by sense amplifier driving signals. In each of the N channel sense amplifiers, an MOSFET is connected between one of bit lines and an interconnection for transmitting a sense amplifier driving signal. In addition, a precharge potential generating circuit for generating a potential of (1/2)V.sub.CC is connected to the interconnection for transmitting the sense amplifier driving signal through a MOSFET. The bit line pairs are equalized by the equalizing MOSFET. Then, in each of the N channel sense amplifiers, the above described interconnection and one of the bit lines are connected to each other, and the above described interconnection and the precharge potential generating circuit are connected to each other.

Abstract: A spare Y decoder is provided with MOS transistors 14 and 20 for charge on both sides of a parasitic resistor 19. As a result, nodes N1 and N2 are rapidly charged by the MOS transistors 20 and 14 for charge, respectively.