Abstract: In a disclosed excess voltage protection circuit, when the input voltage equal to or higher than a predetermined maximum voltage is detected by an excess voltage detection circuit, a switching element is shut off so as to prevent the input voltage being output from the excess voltage protection circuit. A voltage obtained by dividing the input voltage using resistors is output from the excess voltage protection circuit.

Abstract: A disclosed overvoltage protection circuit includes a power source input terminal of an electronic device, the power source input terminal being configured to receive a power source voltage; an internal power source terminal configured to supply power to internal circuits of the electronic device; a voltage blocking circuit connected between the power source input terminal and the internal power source terminal, the voltage blocking circuit being configured to prevent the power source voltage received at the power source input terminal from being provided; and a constant voltage output unit connected in parallel with the voltage blocking circuit, the constant voltage output unit being configured to output a constant voltage. In the event that the power source voltage received at the power source input terminal is higher than or equal to a predetermined voltage, the voltage blocking circuit blocks the power source voltage received at the power source input terminal.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: In a disclosed excess voltage protection circuit, when the input voltage equal to or higher than a predetermined maximum voltage is detected by an excess voltage detection circuit, a switching element is shut off so as to prevent the input voltage being output from the excess voltage protection circuit. A voltage obtained by dividing the input voltage using resistors is output from the excess voltage protection circuit.

Abstract: A power supply system supplies a power to a CPU with a power saving mode to a mobile information device or terminal. The power supply system includes a power supplying circuit for supplying the CPU with a prescribed supply voltage, a voltage detecting circuit for outputting a reset signal resetting the CPU when the supply voltage decreases to be less than or equal to a prescribed reset level, and a control circuit for decreasing the supply voltage to a prescribed power save level when the power saving mode is set. The control circuit decreases the supply voltage to be the prescribed power save level after decreasing the prescribed reset level to be less than or equal to the power save level when the power saving mode is set. The control circuit recovers the prescribed reset level after recovering the supply voltage when the power saving mode is terminated.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A disclosed overvoltage protection circuit includes a power source input terminal of an electronic device, the power source input terminal being configured to receive a power source voltage; an internal power source terminal configured to supply power to internal circuits of the electronic device; a voltage blocking circuit connected between the power source input terminal and the internal power source terminal, the voltage blocking circuit being configured to prevent the power source voltage received at the power source input terminal from being provided; and a constant voltage output unit connected in parallel with the voltage blocking circuit, the constant voltage output unit being configured to output a constant voltage. In the event that the power source voltage received at the power source input terminal is higher than or equal to a predetermined voltage, the voltage blocking circuit blocks the power source voltage received at the power source input terminal.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.

Abstract: A power supply system supplies a power to a CPU with a power saving mode to a mobile information device or terminal. The power supply system includes a power supplying circuit for supplying the CPU with a prescribed supply voltage, a voltage detecting circuit for outputting a reset signal resetting the CPU when the supply voltage decreases to be less than or equal to a prescribed reset level, and a control circuit for decreasing the supply voltage to a prescribed power save level when the power saving mode is set. The control circuit decreases the supply voltage to be the prescribed power save level after decreasing the prescribed reset level to be less than or equal to the power save level when the power saving mode is set. The control circuit recovers the prescribed reset level after recovering the supply voltage when the power saving mode is terminated.