Patents by Inventor Tadayuki Shimizu
Tadayuki Shimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8826856Abstract: An optical thin-film vapor deposition apparatus and method are capable of producing an optical thin-film by vapor depositing a vapor deposition substance onto substrates (14) within a vacuum vessel (10). A dome shaped holder (12) is disposed within the vacuum vessel (10) and holds the substrates (14). A drive rotates the dome shaped holder (12). A vapor depositing source (34) is disposed oppositely to the substrates (14). An ion source (38) irradiates ions to the substrates (14). A neutralizer (40) irradiates electrons to the substrates (14). The ion source (38) is disposed at an angle between an axis, along which ions are irradiated from the ion source (38), and a line perpendicular to a surface of each of the substrates (14). The angle is between 8° inclusive and 40° inclusive. A ratio of a distance in a vertical direction between (i) a center of rotational axis of the dome shaped holder (12), and (ii) a center of the ion source (38), relative to a diameter of the dome shaped holder (12), is between 0.Type: GrantFiled: August 17, 2009Date of Patent: September 9, 2014Assignee: Shincron Co., Ltd.Inventors: Ekishu Nagae, Yousong Jiang, Ichiro Shiono, Tadayuki Shimizu, Tatsuya Hayashi, Makoto Furukawa, Takanori Murata
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Publication number: 20110262656Abstract: A method of vapor depositing a vapor deposition substance onto substrates within a vacuum vessel includes holding the substrates with a dome shaped holder disposed within the vacuum vessel, rotating the dome shaped holder, vapor depositing a substance from a vapor deposition source disposed oppositely to the substrates, supplying ions from an ion source to the substrates, and supplying neutralizing electrons from a neutralizer to the substrates.Type: ApplicationFiled: July 8, 2011Publication date: October 27, 2011Inventors: Ekishu Nagae, Yousong Jiang, Ichiro Shiono, Tadayuki Shimizu, Tatsuya Hayashi, Makoto Furukawa, Takanori Murata
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Publication number: 20110151135Abstract: An optical thin-film vapor deposition apparatus and method are capable of producing an optical thin-film by vapor depositing a vapor deposition substance onto substrates (14) within a vacuum vessel (10). A dome shaped holder (12) is disposed within the vacuum vessel (10) and holds the substrates (14). A drive rotates the dome shaped holder (12). A vapor depositing source (34) is disposed oppositely to the substrates (14). An ion source (38) irradiates ions to the substrates (14). A neutralizer (40) irradiates electrons to the substrates (14). The ion source (38) is disposed at an angle between an axis, along which ions are irradiated from the ion source (38), and a line perpendicular to a surface of each of the substrates (14). The angle is between 8° inclusive and 40° inclusive. A ratio of a distance in a vertical direction between (i) a center of rotational axis of the dome shaped holder (12), and (ii) a center of the ion source (38), relative to a diameter of the dome shaped holder (12), is between 0.Type: ApplicationFiled: August 17, 2009Publication date: June 23, 2011Inventors: Ekishu Nagae, Yousong Jiang, Ichiro Shiono, Tadayuki Shimizu, Tatsuya Hayashi, Makoto Furukawa, Takanori Murata
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Patent number: 6798236Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the first circuit.Type: GrantFiled: October 17, 2002Date of Patent: September 28, 2004Assignee: Renesas Technology Corp.Inventors: Tadayuki Shimizu, Takafumi Takatsuka, Masaki Tsukude
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Patent number: 6714047Abstract: The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.Type: GrantFiled: October 9, 2002Date of Patent: March 30, 2004Assignee: Renesas Technology Corp.Inventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka
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Patent number: 6710634Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.Type: GrantFiled: April 4, 2003Date of Patent: March 23, 2004Assignee: Renesas Technology Corp.Inventors: Shigeki Ohbayashi, Tadayuki Shimizu
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Publication number: 20030201807Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.Type: ApplicationFiled: April 4, 2003Publication date: October 30, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigeki Ohbayashi, Tadayuki Shimizu
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Publication number: 20030193349Abstract: The semiconductor integrated circuit incudes an input circuit which receives a signal, an internal circuit which applies a predetermined function to the received signal, and an output circuit which outputs the signal applied with the predetermined function. An external power supply voltage VDD and an IO power supply voltage VDDQ which is lower than the voltage VDD are supplied to the semiconductor integrated circuit. A voltage VIO obtained by decreasing the external power supply voltage VDD is supplied to the input circuit. The IO power supply voltage VDDQ is supplied to the output circuit.Type: ApplicationFiled: October 9, 2002Publication date: October 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka
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Publication number: 20030193084Abstract: A semiconductor integrated circuit which is supplied with a first power supply voltage and a second power supply voltage from outside so as to operate incorporated circuits, and outputs data at an output terminal, includes an internal circuit that carries out a predetermined function for an input signal, an output circuit which includes a first circuit for converting the signal from the internal circuit into an output signal and a second circuit containing a final stage buffer circuit which outputs, depending on the signal from the first circuit, data to the output terminal; and a switching circuit that switches a power supply voltage supplied to the second circuit, to either the first power supply voltage or the second power supply voltage. A voltage obtained by decreasing the first power supply voltage is supplied to the internal circuit. The first power supply voltage is supplied to the second circuit.Type: ApplicationFiled: October 17, 2002Publication date: October 16, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Takafumi Takatsuka, Masaki Tsukude
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Publication number: 20030183926Abstract: A plurality of semiconductor chips are mounted in the same package, and a power supply is shared by the output circuits of the chips. In this case, even though the internal circuit power supplies of the chips are turned off, since an output circuit is in an ON state, a through current may flow from another chip. Therefore, a circuit for setting transistors constituting the output circuits of the chips in high-impedance states when the power supplies for the internal circuits of the respective semiconductor chips are turned off is added.Type: ApplicationFiled: September 24, 2002Publication date: October 2, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Takafumi Takatsuka, Hirotoshi Sato
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Patent number: 6628559Abstract: The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.Type: GrantFiled: October 9, 2001Date of Patent: September 30, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Minoru Senda
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Patent number: 6584013Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.Type: GrantFiled: October 22, 2001Date of Patent: June 24, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Minoru Senda, Shinichi Kobayashi, Masaki Tsukude, Hirotoshi Sato, Tadayuki Shimizu
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Patent number: 6556485Abstract: An output buffer includes first current driving units connected in parallel between a power-supply voltage and an output node; second current driving units connected in parallel between a ground voltage and an output node; a plurality of operation selection circuits setting the respective first and second current driving units to be in either activated or inactivated state in a non-volatile manner; first signal transmission circuits arranged respectively corresponding to the first current driving circuits and each transmitting the level of output data with a similar first propagation time period; and second signal transmission circuits arranged respectively corresponding to the second current driving units and each transmitting the level of the output data with a similar second propagation time period.Type: GrantFiled: October 9, 2001Date of Patent: April 29, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Hirotoshi Sato, Masaki Tsukude
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Patent number: 6556058Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.Type: GrantFiled: October 11, 2002Date of Patent: April 29, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Ohbayashi, Tadayuki Shimizu
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Publication number: 20030034812Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.Type: ApplicationFiled: October 11, 2002Publication date: February 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigeki Ohbayashi, Tadayuki Shimizu
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Patent number: 6493279Abstract: In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.Type: GrantFiled: October 9, 2001Date of Patent: December 10, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hirotoshi Sato, Masaki Tsukude, Tadayuki Shimizu
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Publication number: 20020159289Abstract: A dynamic-type memory A, a non-volatile memory B and a static-type memory C are enclosed in one package. Separated from a first terminal supplying a power-supply potential to the memories A and B, a second terminal supplying a power-supply potential to the memory C is provided. By stopping the supply of the power-supply potential to the first terminal at stand-by, stand-by current of a semiconductor memory device can be reduced. Therefore, the semiconductor memory device having an increased memory capacity while reducing a mounting area and consumption current at stand-by can be provided.Type: ApplicationFiled: October 22, 2001Publication date: October 31, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Minoru Senda, Shinichi Kobayashi, Masaki Tsukude, Hirotoshi Sato, Tadayuki Shimizu
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Patent number: 6469552Abstract: In a power on reset (POR) circuit, when power is turned on, an output signal of an inverter attains an H level and an N channel MOS transistor is rendered conductive. The potential of an input node of the inverter becomes a potential of a power supply voltage divided by a conductive resistance value R1 of a P channel MOS transistor and a conductive resistance value R2 of an N channel MOS transistor. Assuming that the threshold voltage of the inverter is 0.8 V and R1:R2=2:3, then the power supply voltage Vres at the time when signal POR# inverts its level becomes 1.33 V. Thus, this POR circuit can reliably be utilized even in a product designed to operate with 1.5 V incorporating a MOS transistor having a threshold voltage of 0.8 V.Type: GrantFiled: February 16, 2001Date of Patent: October 22, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Ohbayashi, Tadayuki Shimizu
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Publication number: 20020149985Abstract: The semiconductor memory device of the invention has a refresh timer for generating a refresh clock, a refresh executing circuit for sequentially refreshing a plurality of memory cells part by part on the basis of the cycle of the refresh clock, and a refreshing control circuit disposed between the refresh timer and the refresh executing circuit, for stopping transmission of the refresh clock from the refresh timer to the refresh executing circuit in a predetermined period during which the cycle of the refresh clock is easy to become unstable. With the configuration, an erroneous operation of the refresh executing circuit can be prevented.Type: ApplicationFiled: October 9, 2001Publication date: October 17, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadayuki Shimizu, Masaki Tsukude, Minoru Senda
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Publication number: 20020145925Abstract: In a test mode, a first switch circuit is inactivated, and second and third switch circuits are activated. The oscillation frequency of a ring oscillator can be measured by measuring a delay value from the time a signal is input from a node inputting a test signal to the time it is output through the second switch circuit, inversion and delay circuit and the third switch circuit. Therefore, a semiconductor device capable of a simple measurement of the oscillation frequency can be provided.Type: ApplicationFiled: October 9, 2001Publication date: October 10, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hirotoshi Sato, Masaki Tsukude, Tadayuki Shimizu