Abstract: A method and apparatus for a hybrid network device for performing in a virtual private network (VPN) and a wireless local area network (WLAN) are provided. The hybrid network device comprises a VPN module serving as a VPN hardware accelerator in a WLAN module, which performs in the WLAN, wherein the hybrid network device integrates WLAN and VPN capabilities into one device.

Abstract: A Reconfigurable Key Search Engine is disclosed along with a mobile unit incorporating same and related methods. The RKSE is adapted to efficiently search a memory system storing a plurality of security keys potentially related to multiple networks. One embodiment uses a hierarchical memory system including at least one associative memory.

Abstract: A method and apparatus for a hybrid network device for performing in a virtual private network (VPN) and a wireless local area network (WLAN) are provided. The hybrid network device comprises a VPN module serving as a VPN hardware accelerator in a WLAN module, which performs in the WLAN, wherein the hybrid network device integrates WLAN and VPN capabilities into one device.

Abstract: A method of block-level encryption/decryption for an offset codebook mode of operation during transmission/reception can include: receiving a frame of data to encrypted/decrypted; beginning to divide the frame into at least two packets before receipt of the frame is completed; beginning to divide at least one of the packets into two or more blocks before receipt of the frame is completed; releasing the blocks of the at least one packet for encryption/decryption before receipt of the frame is completed; and enciphering/deciphering the blocks of the at least one packet before receipt of the frame is completed.

Abstract: The present invention relates to a cryptographic apparatus for encrypting data stored in a memory. The cryptographic apparatus of the present invention operates in the ECB, CBC, BCB-MAC, counter and OCB modes using small and simple elements. The cryptographic apparatus minimizes data communication between CPU and the cryptographic apparatus to improve the performance of the communication system. On the other hand, the input buffer and output buffer of the cryptographic apparatus are configured to store at least two blocks respectively, so that the performance of the cryptographic apparatus is maximized. Furthermore, the cryptographic apparatus supports zero-padding, so that the process of the CPU is minimized.

Abstract: Cryptographic systems and methods that support multiple modes of operation, such as CBC, CTR and/or CCM modes. In one aspect, a method for encrypting data includes reading a plaintext data block from a memory, storing the plaintext data block in an input buffer, encrypting the plaintext data block in the input buffer using a first mode to generate a first ciphertext, storing the first ciphertext in an output buffer, encrypting the plaintext data block in the input buffer using a second mode to generate a second ciphertext. For example, in a CCM mode of operation wherein the first mode is a CTR (counter) mode and the second mode is a CBC (cipher block chaining) mode, the block of plaintext that is initially read from memory and stored in the data input register is applied to both the CTR and CBC modes, thereby reducing a number memory read operations as in conventional CCM modes.