Patents by Inventor Tae Ho Choi
Tae Ho Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120214Abstract: An apparatus for fabricating a display panel, the apparatus including: a loading module configured to accommodate a large-area fabricating substrate, the loading module being configured to adjust an inclination of the large-area fabricating substrate from a rear surface of the large-area fabricating substrate and to press the large-area fabricating substrate; and an element transfer module configured to transfer a plurality of light emitting elements or an integrated circuit onto the large-area fabricating substrate and configured to bond and press a wafer on which the plurality of light emitting elements or the at least one integrated circuit is located onto the large-area fabricating substrate.Type: ApplicationFiled: September 18, 2023Publication date: April 11, 2024Inventors: Tae Hee LEE, Kyung Ho KIM, Young Seok SEO, Joo Woan CHO, Byeong Hwa CHOI
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Publication number: 20240120584Abstract: A secondary battery includes: a can having an accommodation space therein; an electrode assembly accommodated in the accommodation space in the can; and a cap assembly sealed with the can. The can has a beading part recessed into a side wall of the can at a region below where the cap assembly is accommodated, and the beading part has an acute angle with respect to the side wall of the can.Type: ApplicationFiled: October 11, 2023Publication date: April 11, 2024Inventors: Jun Ho YANG, Woo Hyuk CHOI, Tae Yoon LEE, Jun Hwan KWON, Joung Ku KIM, Hyun Suk PARK, Dong Sub LEE
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Patent number: 11955611Abstract: An equipment for inspecting a secondary battery is provided. The equipment includes a loading device on which a secondary battery is loaded in an upright position, and a side portion inspecting device which inspects a side portion of the secondary battery loaded on the loading device, wherein the side portion inspecting device comprises an elevation unit which lifts the secondary battery loaded on the loading device so as to be withdrawn out of the loading device and allows the secondary battery to return to its original position after a first period of time elapses and a side portion inspecting unit which captures an image of the side portion of the secondary battery, which is withdrawn out of the loading device by the elevation unit, thereby inspecting the side portion of the secondary battery.Type: GrantFiled: December 23, 2019Date of Patent: April 9, 2024Assignee: LG ENERGY SOLUTION, LTD.Inventors: Tae Young Kim, Dong Hyung Lee, Woo Young Choi, Sang Ho Nam
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Publication number: 20240107002Abstract: A method for coding image information includes generating prediction information by predicting information on a current coding unit, and determining whether the information on the current coding unit is the same as the prediction information. When the information on the current coding unit is the same as the prediction information, a flag indicating that the information on the current coding unit is the same as the prediction information is coded and transmitted. When the information on the current coding unit is not the same as the prediction information, a flag indicating that the information on the current coding unit is not the same as the prediction information and the information on the current coding unit are coded and transmitted.Type: ApplicationFiled: December 6, 2023Publication date: March 28, 2024Applicants: Electronics and Telecommunications Research Institute, University-Industry Cooperation Group of Kyung Hee UniversityInventors: Se Yoon JEONG, Hui Yong KIM, Sung Chang LIM, Jin Ho LEE, Ha Hyun LEE, Jong Ho KIM, Jin Soo CHOI, Jin Woong KIM, Chie Teuk AHN, Gwang Hoon PARK, Kyung Yong KIM, Tae Ryong KIM, Han Soo LEE
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Publication number: 20240096888Abstract: A super-steep switching device and an inverter device using the same are disclosed. The super-steep switching device includes a semiconductor channel disposed on a substrate and made of a semiconductor material having impact ionization characteristic; a source electrode and a drain electrode in contact with the semiconductor channel, wherein the source electrode and the drain electrode are disposed on the substrate and are spaced apart from each other; and a gate electrode disposed on the semiconductor channel so as to overlap only a portion of the semiconductor channel, wherein a top surface of the semiconductor channel includes a first area overlapping the gate electrode, and a second area non-overlapping the gate electrode, wherein a ratio of a length of the first area and a length of the second area is in a range of 1:0.1 to 0.4.Type: ApplicationFiled: September 8, 2022Publication date: March 21, 2024Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITYInventors: Hae Ju CHOI, Tae Ho KANG, Chan Woo KANG, Hyeon Je SON, Jin Hong PARK, Sung Joo LEE, Sung Pyo BAEK
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Patent number: 11930858Abstract: An aerosol generating device according to an aspect comprises a main body that comprises a battery and a controller, a cartridge which is coupled to the main body and comprises a liquid storage that contains liquid composition and an atomization portion that generates an aerosol by heating the liquid composition contained in the liquid storage, and a cover that forms an inner space by being coupled to the main body such that the cartridge is arranged in the inner space, wherein the main body further comprises a light source that emits light toward an inside of the liquid storage, and the cover comprises a window hole through which light entitled from the light source toward the inside of the liquid storage is transmitted to the outside of the cover.Type: GrantFiled: October 6, 2020Date of Patent: March 19, 2024Assignee: KT&G CORPORATIONInventors: Hun Il Lim, Tae Hun Kim, Hyung Jin Jung, Jae Sung Choi, Jung Ho Han
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Publication number: 20240086603Abstract: A method of reinforcement learning of a neural network device for generating a verification vector for verifying a circuit design comprising a circuit block includes inputting a test vector to the circuit block, generating one or more rewards based on a coverage corresponding to the test vector, the coverage being determined based on a state transition of the circuit block based on the test vector, and applying the one or more rewards to a reinforcement learning.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: SAMSUNG ELECTRONICS CO, LTD.Inventors: In HUH, Jeong-hoon KO, Hyo-jin CHOI, Seung-ju KIM, Chang-wook JEONG, Joon-wan CHAI, Kwang-II PARK, Youn-sik PARK, Hyun-sun PARK, Young-min OH, Jun-haeng LEE, Tae-ho LEE
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Patent number: 11923035Abstract: A pseudo dual port memory device in which an operating speed is improved and stability is increased is provided. The pseudo dual port memory device may include a memory cell, a pair of bit lines connected to the memory cell, a write driver, a sense amp, and a column multiplexer which is connected to the bit lines, receives a write multiplexer control signal and a read multiplexer control signal, connects the bit lines to the write driver in response to the write multiplexer control signal, and connects the bit lines to the sense amp in response to the read multiplexer control signal. A precharge control signal generation circuit which is connected to the column multiplexer may generate a precharge control signal on the basis of the read and write multiplexer control signals, and a bit line precharge circuit may precharge the bit lines based on the precharge control signal.Type: GrantFiled: February 10, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Chan Ho Lee, Tae Min Choi, Jeong Kyun Kim, Hyeong Cheol Kim, Suk Youn, Ju Chang Lee, Kyu Won Choi
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Publication number: 20240066564Abstract: Proposed are a substrate processing apparatus and a substrate processing method capable of efficiently preventing contamination of a substrate and a processing space caused by a reverse flow of purge gas.Type: ApplicationFiled: March 27, 2023Publication date: February 29, 2024Applicant: SEMES CO., LTD.Inventors: Do Hyung KIM, Dae Hun KIM, Young Jin KIM, Tae Ho KANG, Young Joon HAN, Eun Hyeok CHOI, Jun Gwon LEE
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Publication number: 20240069524Abstract: Disclosed is an apparatus for excitation signal generation for a resolver. The apparatus includes a sine wave generator that generates a sine wave based on a square wave, an amplifier that amplifies the sine wave, a differential signal generator that converts, into a differential signal, the amplified sine wave, a driver that inputs the differential signal to a coil, and a processor that generates an excitation signal by increasing a voltage of the sine wave from a start voltage to a target voltage through at least one of the sine wave generator and the amplifier based on a transient current that flows into the coil in a transient response interval.Type: ApplicationFiled: December 27, 2022Publication date: February 29, 2024Applicant: HYUNDAI MOBIS CO., LTD.Inventors: Yun Ho CHOI, Hyung Min PARK, Joo Won PARK, Yeon Ho KIM, Won Hee JO, Tae Hwan KANG, Beom Cheol CHO
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Patent number: 11913098Abstract: A self-healing alloy contains 5 to 11% by weight of molybdenum (Mo), iron (Fe) as a remainder, and unavoidable impurities. A method for manufacturing the self-healing alloy includes heat treating the alloy or preparing an alloy raw material powder and sintering, homogenizing, and cooling the alloy raw material powder.Type: GrantFiled: March 22, 2021Date of Patent: February 27, 2024Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, Kookmin University Industry Academy Cooperation FoundationInventors: Kyung Sik Choi, Hoo Dam Lee, Tae Gyu Lee, Byung Ho Min, Young Jun Kwon, Keun Won Lee, Yoon Jung Won, Ki Sub Cho
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Publication number: 20210205354Abstract: An anti-inflammatory composition according to an embodiment includes natural organic calcium carbonate, and thus provides the advantages that the composition can be consumed as food, is completely harmless to the human body, and can significantly treat or alleviate inflammations in human and animal cells. Also, the anti-inflammatory composition can promote metabolisms of cells and eliminate active oxygen in the body while treating inflammations. Since the anti-inflammatory composition can be preserved easily because it is not sensitive to the surrounding environment and is resistant to degradation even when exposed to the atmosphere, the anti-inflammatory composition can be added to various beverages or food materials. Furthermore, when the anti-inflammatory composition is added to food materials, a high degree of freshness of food can be preserved for a long time by preventing the oxidation thereof, and also has the effect of restoring oxidized skin and damaged skin through reduction.Type: ApplicationFiled: October 18, 2018Publication date: July 8, 2021Inventors: Tae Ho CHOI, Young Hyuk JUNG, Young Yong IN, Jin Sol CHOI, Bo Mi KIM
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Patent number: 9281202Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.Type: GrantFiled: October 23, 2009Date of Patent: March 8, 2016Assignee: MagnaChip Semiconductor, Ltd.Inventors: Tae-Ho Choi, Jung-Hwan Lee, Heung-Gee Hong, Jeong-Ho Cho, Min-Wan Choo, Il-Seok Han
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Publication number: 20100270605Abstract: A nonvolatile memory cell and a method for fabricating the same can secure stable operational reliability as well as reducing a cell size. The nonvolatile memory cell includes a drain region formed in a substrate, a source region formed in the substrate to be separated from the drain region, a floating gate formed over the substrate between the drain region and the source region, a halo region formed in the substrate in a direction that the drain region is formed, a dielectric layer formed on sidewalls of the floating gate, and a control gate formed over the dielectric layer to overlap with at least one sidewall of the floating gate.Type: ApplicationFiled: October 23, 2009Publication date: October 28, 2010Inventors: Tae-Ho CHOI, Jung-Hwan Lee, Heung-Gee Hong, Jeong-Ho Cho, Min-Wan Choo, Il-Seok Han
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Publication number: 20080149995Abstract: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.Type: ApplicationFiled: February 4, 2008Publication date: June 26, 2008Inventor: Tae Ho Choi
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Patent number: 7348242Abstract: A method of fabricating a nonvolatile memory device including forming a plurality of device isolation layers in a semiconductor substrate to define a plurality of active regions, sequentially depositing an insulating layer and a first conductive layer on the semiconductor substrate, and forming a hard mask pattern on the first conductive layer. The method also includes forming a plurality of floating gates on the insulating layer by etching the first conductive layer using the hard mask pattern as a mask, forming a tunnel insulating layer on the semiconductor substrate including floating gates and the insulating layer, and depositing a second conductive layer on the tunnel insulating layer. The method further includes forming a plurality of control gate electrodes across the active regions by etching the second conductive layer, forming source and drain regions in the semiconductor substrate by performing an ion implantation, and forming contacts in the drain regions.Type: GrantFiled: December 30, 2004Date of Patent: March 25, 2008Assignee: Dongbu HiTek Co., Ltd.Inventor: Tae Ho Choi
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Patent number: 7247917Abstract: Nonvolatile semiconductor memory devices and methods of manufacturing the same are disclosed. A disclosed nonvolatile semiconductor memory cell includes a semiconductor substrate; first and second semiconductor cells positioned on the semiconductor substrate at a distance from each other; a first source and a second source adjacent the first and second semiconductor cells; a first drain contact between the first and second semiconductor cells; first and second cap dielectrics formed on the first and second semiconductor cells, respectively; first and second sidewall spacers formed on sidewalls of the first and second semiconductor cells, respectively; an inter metal dielectric layer covering the first and second cap dielectrics and the first and second sidewall spacers, a drain contact hole exposing the drain; and a second drain contact connected to the first drain contact through the drain contact hole.Type: GrantFiled: December 27, 2004Date of Patent: July 24, 2007Assignee: Dongbu Electronics Co., Ltd.Inventor: Tae Ho Choi
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Patent number: 7153742Abstract: A flash memory device fabrication method is disclosed. A disclosed method comprises: forming an oxide layer on a substrate; depositing a first polysilicon on the entire surface of the oxide layer and patterning the first polysilicon; depositing an insulating layer on the entire surface of the first polysilicon and patterning the insulating layer to expose the first polysilicon; depositing a second polysilicon on the entire surface of the resulting structure and patterning the second polysilicon; removing the insulating layer; depositing a dielectric layer on the entire surface of the resulting structure; and depositing a third polysilicon on the entire surface of the dielectric layer.Type: GrantFiled: December 29, 2004Date of Patent: December 26, 2006Assignee: Dongbu Electronics Co., Ltd.Inventor: Tae Ho Choi
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Patent number: 6844232Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.Type: GrantFiled: October 7, 2003Date of Patent: January 18, 2005Assignee: Anam Semiconductor, Inc.Inventors: Tae Ho Choi, Jae Yeong Kim
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Publication number: 20040071025Abstract: A cell transistor of a flash memory device includes a semiconductor substrate, a source region, a drain region, a floating gate, an inter-gate insulating layer, and a control gate, wherein the floating gate has a tip protruding into an end portion of the source region. With the application of erasing voltages to the source region and the control gate, an intense electric field is induced on the tip of the floating gate. Accordingly, an erasing efficiency of the cell transistor can be enhanced.Type: ApplicationFiled: October 7, 2003Publication date: April 15, 2004Applicant: ANAM Semiconductor, Inc.Inventors: Tae Ho Choi, Jae Yeong Kim