Abstract: The disclosure relates to a functional membrane, a microfluidic chip including the same, and a method of manufacturing the microfluidic chip. The functional membrane according to an embodiment includes a membrane having one or more pores, and a coating material covering the pores, on at least one surface of the membrane.

Abstract: The simulation system for predicting heating and cooling loads of a building comprises the collection unit collecting measurement data of a target building from a BEMS, the identification unit identifying indoor and outdoor temperature, humidity, and insolation measured in the building in real time based on RTS method, the correlation derivation unit deriving a correlation between energy usage based on the BEMS measurement data collected by the collection unit and the cooling and heating loads according to indoor and outdoor temperature, humidity, and insolation identified by the identification unit, the simulation unit predicting a change in cooling and heating loads according to a change in at least one of pieces of measurement data based on the correlation derived from the correlation derivation unit to perform a simulation, and the information provision unit providing a simulation result from the simulation unit in a visible form to a user terminal.

Abstract: A novel compound for a capping layer, and an organic light-emitting device containing the same are disclosed.

Abstract: A display apparatus according to a concept of the disclosure includes: a display panel configured to display an image in a front direction; a top chassis positioned in a front direction of the display panel; a bottom chassis positioned in a rear direction of the display panel; a rear cover covering a rear side of the bottom chassis; and a stand member being accommodatable in the rear cover and selectively coupled with a rear surface of the rear cover, wherein the rear cover includes an accommodating portion in which the stand member is accommodated and a coupling portion coupled with the stand member, and the stand member includes an inserting protrusion which is inserted into the accommodating portion and the coupling portion.

Abstract: A system for predicting a negative pressure of a brake booster of a vehicle includes: a driving information detector detecting driving information related to driving of the vehicle; and a controller determining a negative pressure of an intake manifold based on a pressure of the intake manifold and an atmospheric pressure which is the driving information and including a booster negative pressure predictor predicting the negative pressure of the brake booster by integrating over time a change rate according to a charging rate and a discharging rate of the negative pressure determined using a negative pressure of the brake booster determined in a previous cycle according to a logic for predicting the negative pressure of the brake booster and the negative pressure of the intake manifold of a current cycle and an imitated brake pedal force signal of the current cycle imitating an acceleration of the vehicle.

Abstract: An apparatus for diagnosing a fault of a vehicle component, may include: a processor; a memory storing one or more programs configured to be executed by the processor; and the one or more programs include instructions for: an acceleration sensor for detecting an acceleration signal; feature extraction unit for extracting features related to a fault of a vehicle component from the detected acceleration signal; and a machine learning model for diagnosing a fault of the vehicle component based on the extracted features, wherein the machine learning model may be a model selected according to a preset evaluation index among a plurality of machine learning models trained based on training data sets.

Abstract: A display device includes a substrate including an emission area and a non-emission area, alignment electrodes arranged to be spaced from each other in a first direction on the substrate and extending in a second direction crossing the first direction, and pixels arranged along the second direction. Pixels adjacent to each other in the second direction from among the pixels may be configured to emit light of different colors. Each of the pixels may include first light emitting elements on the alignment electrodes and arranged along the second direction, second light emitting elements on the alignment electrodes, spaced from the first light emitting elements in the first direction, and arranged along the second direction, a first pixel electrode electrically connected to a first driving power and first ends of the first light emitting elements, a second pixel electrode spaced from the first pixel electrode in the first direction.

Abstract: A display device may include pixels on a substrate. Each of the pixels may include: a first alignment electrode and a second alignment electrode located on the substrate and spaced from each other; a first insulating layer on the first alignment electrode and the second alignment electrode; a light emitting element located on the first insulating layer between the first and second alignment electrodes; a dummy pattern located between the first insulating layer and the light emitting element; a second insulating layer located on the light emitting element and exposing first and second ends of the light emitting element; a first electrode electrically connected to the first end of the light emitting element; and a second electrode spaced from the first electrode, and electrically connected to the second end of the light emitting element. The dummy pattern may include a same material as the second insulating layer.

Abstract: A display device includes: light emitting elements, each of the light emitting elements including a first end having a first polarity and a second end having a second polarity different from the first polarity; and a first type connection electrode contacting the first ends and/or the second ends of the light emitting elements, wherein a first type connection electrode includes: a middle portion extending in a first direction; a first electrode portion extending from the middle portion toward a first side in a second direction intersecting the first direction; a second electrode portion extending from the middle portion toward the first side in the second direction and spaced from the first electrode portion by a first width in the first direction; a third electrode portion extending from the middle portion toward a second side in the second direction; and a fourth electrode portion.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.

Abstract: The present technology relates to an electronic device. A memory device according to an embodiment includes a memory cell string including first memory cells included in a first channel area, second memory cells included in a second channel area, and dummy memory cells connected between the first memory cells and the second memory cells, a peripheral circuit configured to perform a program operation of storing data in the first to second memory cells, and a program operation controller configured to control the peripheral circuit to apply a first pass voltage to a dummy word line connected to the dummy memory cells during the program operation, apply a second pass voltage less than the first pass voltage to the dummy word line, and then apply a program voltage to a selected word line among a plurality of word lines connected to the first and second memory cells.

Abstract: A memory device includes a memory structure including at least one non-volatile memory cell capable of storing multi-bit data, and a control device configured to perform a program verification after a first program pulse is applied to the at least one non-volatile memory cell, determine a program mode for the at least one non-volatile memory cell based on a result of the program verification, and change a level of a pass voltage, applied to another non-volatile memory cell coupled to the at least one non-volatile memory cell, from a first level to a second level which is higher than the first level, or a setup time for changing a potential of a bit line coupled to the at least one non-volatile memory cell, according to the program mode.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: A memory device includes a controller that performs a program verification after a first program pulse is applied to the at least one non-volatile memory cell. The first program pulse is applied during a data program operation and the data program operation includes applying program pulses to program multi-bit data to the at least one non-volatile memory cell. The controller also determines a program mode for the at least one non-volatile memory cell based on a result of the program verification, and changes at least one of a level of a first control voltage based on the program mode. The first control voltage is applied to a drain select line coupled to the at least one non-volatile memory cell.

Abstract: Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases.

Abstract: A nonvolatile memory device comprising: a cell string comprising a plurality of memory cells, a bit line coupled to the cell string, and a page buffer suitable for precharging the bit line, a first sensing node and a second sensing node to a preset level in a first period, and double-sensing the bit line through the first and second sensing nodes in a second period, wherein the page buffer comprises: a first coupling unit suitable for coupling the bit line and the first sensing node, a second coupling unit suitable for coupling the first and second sensing nodes, and controlling the first and second sensing nodes to have a voltage level interval according to a preset ratio in the second period, a first and second latch units suitable for latching a logic levels corresponding to a voltage levels of the first and second sensing nodes, respectively.

Abstract: Provided is a memory device. The memory device may include a voltage code controller configured to generate a voltage code that generates a program voltage and pass voltages based on a number of times a program loop is performed, and a voltage generator configured to generate the program voltage and the pass voltages in response to the voltage code, transmit the program voltage to a selected word line, and transmit the pass voltages to unselected word lines, wherein the voltage generator is configured to sequentially increase the pass voltage that is applied to the unselected word lines in order of proximity to the selected word line as the number of times a program loop is performed increases.

Abstract: The present invention relates to a skin preparation composition for external use having excellent antiseptic ability without using chemical antiseptics. More particularly, the present invention relates to a skin preparation composition for external use, comprising: glyceryl undecylenate having excellent antiseptic ability; and one or more mixtures of ethylhexylglycerin, glyceryl caprylate, p-anisic acid and a citrus mixed extract, thus improving antiseptic ability through the increased effects of antiseptic abilities of those materials.

Abstract: The present invention relates to a phytospingosine derivative generated by a condensation reaction of phytospingosine and maltose or lactose, which is an aldose-based disaccharide, and to a composition containing the same. The phytospingosine derivative of the present invention has high solubility in water compared with phytospingosine, is easy to formulate since the stabilization problem in a solution is solved, and maintains or further enhances the antibacterial effect of phytospingosine.