Patents by Inventor Tae-Hwan Oh
Tae-Hwan Oh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11990361Abstract: The chuck for supporting a target substrate for a display device, the chuck includes: a base having a first surface to support an object and a second surface opposite the first surface, the first surface including a first area and a second area; and indentations formed in the second area and recessed from the first area in a thickness direction of the base. The indentations include a first indentation extending in a first direction and a second indentation extending in a second direction intersecting the first direction.Type: GrantFiled: July 1, 2021Date of Patent: May 21, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Hee Sun Jang, Tae Hun Kim, Do Hwan Kim, Jae Han Kim, Seung Ho Myoung, Dae Young Oh, Gyeong Hee Han
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Patent number: 11985848Abstract: A touch display device exhibiting low reflectivity is disclosed. The touch display device includes a light-blocking stack composed of at least two light-blocking color layers overlapping a plurality of touch electrodes disposed on an encapsulation unit, and a low-reflection layer disposed on the light-blocking stack, thereby absorbing external light without a separate polarizing plate, thus exhibiting low reflectivity.Type: GrantFiled: April 11, 2022Date of Patent: May 14, 2024Assignee: LG Display Co., Ltd.Inventors: Jae-Young Oh, Tae-Hwan Kim
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Publication number: 20240112002Abstract: Disclosed is an interface system including a first neuron cluster that outputs a first neuron signal including a first neuron request and first neuron data by performing a first arithmetic operation, and a first interface circuit that stores the first neuron data and outputs a first response, in response to the first neuron request. The first neuron cluster outputs a second neuron signal including a second neuron request and second neuron data by performing a second arithmetic operation, in response to the first response. Before the first data is transmitted to a second neuron cluster different from the first neuron cluster, the first interface circuit outputs the first response in response to a fact that the first neuron data is stored.Type: ApplicationFiled: June 29, 2023Publication date: April 4, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Eun KIM, Tae Wook KANG, Hyuk KIM, Young Hwan BAE, Kyung Jin BYUN, Kwang IL OH, Jae-Jin LEE, In San JEON
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Publication number: 20240113304Abstract: Disclosed is a cathode for a lithium secondary battery, which has a coating layer formed on an edge portion of a cathode plate, a method of manufacturing the cathode, and a lithium secondary battery including the cathode. The cathode includes a cathode plate and a coating layer formed at an edge portion of the cathode plate, in which the cathode plate includes a cathode current collector provided with cathode tab and a cathode active material laminated on at least one surface of the cathode current collector, and the coating layer includes a conductive polymer layer and an insulating coating layer.Type: ApplicationFiled: July 3, 2023Publication date: April 4, 2024Inventors: Won Joon JANG, Hyun Je KIM, Tae Seob OH, Seong Hwan LEE, Seung Taek LEE, Chan Sub LEE
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Publication number: 20240097799Abstract: Disclosed is an amplification circuit, which includes a first amplifier that receives an external signal and performs first band pass filtering on the external signal to output a first filter signal, and a second amplifier that receives the first filter signal and performs second band pass filtering on the first filter signal to output a second filter signal, and a frequency pass bandwidth of the second band pass filtering is narrower than a frequency pass bandwidth of the first band pass filtering.Type: ApplicationFiled: June 26, 2023Publication date: March 21, 2024Applicant: Electronics and Telecommunications Research InstituteInventors: Sung Eun KIM, Tae Wook KANG, Hyuk KIM, Kyung Hwan PARK, Mi Jeong PARK, Hyung-IL PARK, Kyung Jin BYUN, Kwang IL OH, Jae-Jin LEE, In Gi LIM
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Publication number: 20240088373Abstract: A high-nickel positive electrode active material and a method of making the same is disclosed herein. In some embodiments, the material includes a lithium transition metal oxide, wherein the lithium transition metal oxide is secondary particles, wherein each secondary particle is an aggregate of primary particles, and wherein the oxide has an amount of nickel of 80 atm % or more, a first coating layer formed on a surface of the secondary particle and on surfaces of a portion or all of the primary particles, the first coating layer contains nickel and manganese, and has a layered structure, and a second coating layer formed on an outer surface of the first coating layer, the second coating layer contains boron. The active material has improved stability and initial capacity and crack generation at an interface between primary particles is also suppressed.Type: ApplicationFiled: March 23, 2022Publication date: March 14, 2024Applicant: LG Chem, Ltd.Inventors: Tae Hwan Jun, Hae Jong Jung, Gyun Joong Kim, Myoung Hwan Oh
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Patent number: 11923882Abstract: A hybrid communication device, an operation method thereof, and a communication system including the same are provided. The hybrid communication device includes a contact unit that includes an antenna for receiving a first communication signal and an electrode for receiving a second signal, a switch controller that includes a first switch and a second switch and controls the first switch and the second switch based on a change in capacitance of the electrode, and a signal processing unit that receives at least one of the first communication signal and the second communication signal from the contact unit via the first switch and processes the received signal. The first switch is connected to the contact unit, and the signal processing unit is connected to the first switch.Type: GrantFiled: March 25, 2021Date of Patent: March 5, 2024Assignee: Electronics and Telecommunications Research InstituteInventors: Tae Wook Kang, Sung Eun Kim, Hyung-Il Park, Jae-Jin Lee, Hyuk Kim, Kyung Hwan Park, Mi Jeong Park, Kyung Jin Byun, Kwang Il Oh, In Gi Lim
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Patent number: 11912120Abstract: A battery mounting structure for a vehicle is provided to include a case having a first internal member that is disposed to be spaced parallel to an upper side of a lower panel of the case and a second internal member that is disposed perpendicular to the first internal member, and configured to accommodate a plurality of battery modules therein using the first internal member and the second internal member. An outer side member is provided in a shape protruding toward the outside on an outer side of the case. The battery modules are disposed in a stacking direction of battery cells that is parallel to a longitudinal direction of the first internal member.Type: GrantFiled: September 22, 2020Date of Patent: February 27, 2024Assignees: Hyundai Motor Company, Kia Motors CorporationInventors: Yong Hwan Choi, Yu Ri Oh, Tae Hyuck Kim, Gyung Hoon Shin, Hae Kyu Lim, Ji Woong Jung
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Publication number: 20230116475Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.Type: ApplicationFiled: December 14, 2022Publication date: April 13, 2023Inventors: SUNG SIK PARK, San Jin KIM, Tae Hwan OH, Hyun Jeong LEE, Sung Jin JANG, Gyu Min JEONG
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Patent number: 11552167Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.Type: GrantFiled: June 30, 2021Date of Patent: January 10, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung Sik Park, Sang Jin Kim, Tae Hwan Oh, Hyun Jeong Lee, Sung Jin Jang, Gyu Min Jeong
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Publication number: 20220013630Abstract: A semiconductor device includes first and second active patterns extending in a first direction, a first epitaxial pattern on the first active pattern and adjacent to the second active pattern, a second epitaxial pattern on the second active pattern and adjacent to the first active pattern, an element separation structure separating the first and second active patterns between the first and second epitaxial patterns, and including a core separation pattern, and a separation side wall pattern on a side wall of the core separation pattern, and a gate structure extending in a second direction intersecting the first direction, on the first active pattern. An upper surface of the gate structure is on the same plane as an upper surface of the core separation pattern. The separation side wall pattern includes a high dielectric constant liner, which includes a high dielectric constant dielectric film including a metal.Type: ApplicationFiled: June 30, 2021Publication date: January 13, 2022Inventors: Sung Sik Park, Sang Jin Kim, Tae Hwan Oh, Hyun Jeong Lee, Sung Jin Jang, Gyu Min Jeong
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Patent number: 10643888Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.Type: GrantFiled: June 13, 2017Date of Patent: May 5, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
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Patent number: 10338134Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.Type: GrantFiled: October 25, 2016Date of Patent: July 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Min-Chul Jun, Yun-Bo Yang, Dong-Ho Lee, Tae-Hwan Oh, Dong-Han Yoon
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Publication number: 20170278745Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.Type: ApplicationFiled: June 13, 2017Publication date: September 28, 2017Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
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Patent number: 9711395Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.Type: GrantFiled: July 28, 2015Date of Patent: July 18, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
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Publication number: 20170194210Abstract: A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces ofType: ApplicationFiled: October 13, 2016Publication date: July 6, 2017Inventors: Tae-hwan OH, Kwang-sub YOON, Yong-chul JEONG, Seung-ho OH, Ji-young CHOI, Suk-won LEE, Woo-jeong SHIN, Myoung-ki JUNG, Min-jung KIM
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Publication number: 20170139004Abstract: In an interface board for testing a multichip package, the multichip package includes a first type semiconductor chip and a second type semiconductor chip, the interface board includes a first surface facing the multichip package and a second surface facing a test apparatus, the first surface includes upper terminals that are electrically connected to terminals of the multichip package, the second surface includes lower terminals that are electrically connected to the test apparatus, and the upper terminals include a first upper terminal group for testing the first type semiconductor chip and a second upper terminal group for testing whether a crack defect exists in the second type semiconductor chip.Type: ApplicationFiled: October 25, 2016Publication date: May 18, 2017Inventors: MIN-CHUL JUN, YUN-BO YANG, DONG-HO LEE, TAE-HWAN OH, DONG-HAN YOON
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Publication number: 20160035617Abstract: In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are formed on the substrate in the circuit area such that the overlay mark area is free of the gate patterns, and conductive contact patterns are formed on the substrate between the gate patterns in the circuit area. A mirror pattern is formed on the substrate in the overlay mark area, where the mirror pattern and the contact patterns comprising a same reflective material. Related semiconductor devices, overlay marks, and fabrication methods are also discussed.Type: ApplicationFiled: July 28, 2015Publication date: February 4, 2016Inventors: Jong-Su Kim, Dong-Woon Park, Tae-Hoi Park, Yong-Kug Bae, Tae-Hwan Oh, Chang-Hoon Lee, Boo-Hyun Ham
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Patent number: 9123655Abstract: A method of manufacturing a layer pattern of a semiconductor device, the method including forming an anti-reflective coating (ARC) layer on an etching object layer such that the ARC layer includes a polymer having an imide group; forming a photoresist pattern on the ARC layer; wet etching portions of the ARC layer exposed by the photoresist pattern to form an ARC layer pattern; and etching the etching object layer using the photoresist pattern as an etch mask to form the layer pattern.Type: GrantFiled: February 26, 2014Date of Patent: September 1, 2015Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-Hwan Oh, Yu-Ra Kim, Tae-Sun Kim, Kwang-Sub Yoon
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Publication number: 20140303256Abstract: The present invention relates to a pharmaceutical composition for the prevention and treatment of blood-brain barrier disorder comprising fluoxetine as an active ingredient. More particularly, fluoxetine inhibits the expressions of matrix metalloproteinase(MMP)-2, MMP-9, and MMP-12, which are reported to be related to blood-brain barrier (BBB) disruption and inflammatory reaction after spinal cord injury, specifically inhibits the activations of MMP-2 and MMP-9, inhibits the decomposition of ZO-1, the most representative tight junction protein, so as to maintain tight junction between endothelial cells and to protect blood-brain barrier thereby, inhibits the increase of blood-brain barrier permeability, and inhibits the expressions of chemoattractants of blood cells, such as CXCL-1, CXCL-2, CCL-2, CCL-3 and CCL-4 so as to reduce inflow of blood into spinal cord and recover exercise function which has been deteriorated by spinal cord injury.Type: ApplicationFiled: October 19, 2012Publication date: October 9, 2014Applicant: UNIVERSITY INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITYInventors: Tae Young Yune, Tae Hwan Oh, Hyung Hwan Baik, Jee Youn Lee