Abstract: A home port for a semiconductor manufacturing nozzle head includes a body having a discharge space configured to receive treatment liquid discharged from a plurality of nozzles, discharge flow passages connected to be in communication with the discharge space and penetrating through the body so as to face the plurality of nozzles, and a cleaning liquid distribution system, which is formed to penetrate through the body, and is connected to transfer a cleaning liquid to the discharge flow passages. The cleaning liquid distribution system includes supply flow passages connected to supply the cleaning liquid to the discharge flow passages, and a lead-in passage connected to and which joins the supply flow passages, and connected to receive the cleaning liquid injected from the outside.

Abstract: Disclosed are a backside illuminated image sensor and a method of manufacturing the same. More particularly, a backside illuminated image sensor and a method of manufacturing the backside illuminated image sensor include a light scattering portion in a substrate configured to converge a path of incident light to a photoelectric conversion structure, thereby preventing cross-talk between adjacent pixels and increasing light sensitivity.

Abstract: Disclosed are a backside illuminated image sensor and a method of manufacturing the same. More particularly, a backside illuminated image sensor and a method of manufacturing the backside illuminated image sensor include a plurality of sequential layers have different refractive indexes to extend a path of incident light passing through a lens, thereby increasing sensitivity.

Abstract: A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure.

Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.

Abstract: A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure.

Abstract: A semiconductor device includes a substrate having a cell region and a connection region. A plurality of gate electrodes is stacked in a vertical direction in the cell region of the substrate. Conductive pads that are electrically connected to a peripheral circuit extend horizontally from the gate electrodes to the connection region. The conductive pads form a cascade structure in the connection region. Contact plugs that have different vertical lengths are electrically connected to respective ones of the conductive pads. The conductive pads have contact portions that are thicker in the vertical direction than the gate electrodes.

Abstract: A semiconductor device including a plug; a lower insulating film surrounding a lower sidewall of the plug; a spacer surrounding an upper sidewall of the plug; and a first interconnection line on the plug, the lower insulating film, and the spacer, the first interconnection line being in contact with an upper surface of the plug, wherein an upper portion of the spacer protrudes higher than the upper surface of the plug.