Abstract: A touch sensing unit includes first touch electrodes, a first touch signal line, and a second touch signal line. The first touch electrodes are disposed in a touch sensor area. The first touch signal line is electrically connected to some of the first touch electrodes arranged in a first column. The second touch signal line is electrically connected to some of the first touch electrodes arranged in a second column different from the first column. The second touch signal line includes a first bent portion bent at least once in an intersection region of the first touch signal line and the second touch signal line.

Abstract: A touch unit is provided including a touch electrode disposed in a sensor region. A touch driving wire is connected to the touch electrode. The touch driving wire includes a first routing line connected to a first side of the touch electrode and a second routing line branched from the first routing line and connected to a second side of the touch electrode. A pad electrode line is spaced apart from the touch driving wire. The pad electrode line is connected to a pad. A pad connection line is connected to the touch driving wire and the pad electrode line. The pad connection line is disposed in a different layer from the touch driving wire. An area in which the pad connection line is in contact with the first routing line is greater than an area in which the pad connection line is in contact with the pad electrode line.

Abstract: A touch sensor may include a base layer, a sensing electrode set, a first insulating layer, a first conductive member, and a second insulating layer. The sensing electrode set may be disposed on the base layer, may include a first first-type sensing electrode, and may include a first second-type sensing electrode. The first insulating layer may be disposed on the sensing electrode set, may include a contact hole, and may include a first opening. The first conductive member may be disposed on the first insulating layer and may be directly connected to the first second-type sensing electrode through the contact hole. The second insulating layer may be disposed on the first insulating layer, may cover the first conductive member, and may include a second opening. Each of the first opening and the second opening may partially expose the first first-type sensing electrode or the first second-type sensing electrode.

Abstract: A display apparatus includes a display panel receiving light from a light source. The display panel includes a liquid crystal panel, first and second polarizers respectively disposed on front and rear sides of the liquid crystal panel, and an optical layer disposed on a front surface of the second polarizer. The optical layer includes a first resin layer having light absorption portions for absorbing a portion of incident light, a second resin layer disposed on a front surface of the first resin layer, the second resin layer having a higher refractive index than the first resin layer, the second resin layer having light diffusion portions for diffusing light not absorbed by the light absorption portions.

Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: A touch sensing unit includes first touch electrodes, a first touch signal line, and a second touch signal line. The first touch electrodes are disposed in a touch sensor area. The first touch signal line is electrically connected to some of the first touch electrodes arranged in a first column. The second touch signal line is electrically connected to some of the first touch electrodes arranged in a second column different from the first column. The second touch signal line includes a first bent portion bent at least once in an intersection region of the first touch signal line and the second touch signal line.

Abstract: A semiconductor device includes a time-to-digital converter (TDC) that receives a reference frequency signal and a feedback frequency signal, and outputs a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal; a digital loop filter (DLF) that outputs a second digital signal generated by filtering the first digital signal; a multiplier circuit that outputs one of a third digital signal and a final test signal, the third digital signal generated by performing a multiplication operation on the second digital signal using a multiplication coefficient; a digital-controlled oscillator (DCO) that generates an oscillation signal having a frequency based on the output one of the third digital signal and the final test signal; and a loop gain calibrator (LGC) that receives the oscillation signal, generates a pair of test signals, and determines the multiplication coefficient using the pair of test signals.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A digitally-controlled oscillator (DCO) includes a current mirror configured to generate a reference current at a first output terminal thereof, and a supply current having a magnitude proportional to a magnitude of the reference current at a second output terminal thereof. An oscillation circuit is provided, which is responsive to the supply current at an input node thereof. This oscillation circuit generates a periodic output signal having a frequency that varies in response to changes in the magnitude of the supply current. A variable resistance circuit is provided, which is responsive to a first control signal having a magnitude that influences a value of a resistance provided between a first node thereof, which receives the reference current, and a second node thereof.

Abstract: A phase locked loop circuit includes a voltage controlled oscillator configured to output a clock signal having a predetermined frequency based in a control voltage, a phase frequency detector configured to compare the clock signal with a reference signal to output a first control signal and a second control signal, a charge pump configured to output the control voltage based on the first control signal and the second control signal, a voltage supply including an output terminal connected to an output terminal of the charge pump by a transmission switch, and a leakage remover circuit connected to the transmission switch and configured to remove a leakage current flowing through the transmission switch while the transmission switch is turned-off.

Abstract: A semiconductor device includes a time-to-digital converter (TDC) that receives a reference frequency signal and a feedback frequency signal, and outputs a first digital signal indicating a time difference between the reference frequency signal and the feedback frequency signal; a digital loop filter (DLF) that outputs a second digital signal generated by filtering the first digital signal; a multiplier circuit that outputs one of a third digital signal and a final test signal, the third digital signal generated by performing a multiplication operation on the second digital signal using a multiplication coefficient; a digital-controlled oscillator (DCO) that generates an oscillation signal having a frequency based on the output one of the third digital signal and the final test signal; and a loop gain calibrator (LGC) that receives the oscillation signal, generates a pair of test signals, and determines the multiplication coefficient using the pair of test signals.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A display apparatus includes a display panel receiving light from a light source. The display panel includes a liquid crystal panel, first and second polarizers respectively disposed on front and rear sides of the liquid crystal panel, and an optical layer disposed on a front surface of the second polarizer. The optical layer includes a first resin layer having light absorption portions for absorbing a portion of incident light, a second resin layer disposed on a front surface of the first resin layer, the second resin layer having a higher refractive index than the first resin layer, the second resin layer having light diffusion portions for diffusing light not absorbed by the light absorption portions.

Abstract: A clock jitter measurement circuit includes: an internal signal generator configured to generate a single pulse signal and an internal clock signal which are both synchronized with an input clock signal received by the clock jitter measurement circuit, a plurality of edge delay cells serially connected to each other and configured to generate a plurality of edge detection signals respectively corresponding to a plurality of delay edges obtained by delaying an edge of the internal clock signal, a plurality of latch circuits configured to latch the single pulse signal in synchronization with the plurality of edge detection signals and output a plurality of sample signals, and a count sub-circuit configured to count a number of activated sample signals of the plurality of sample signals and output a count value based on the counted number of activated sample signals.

Abstract: A circuit for measuring clock jitter includes: an internal signal generator configured to generate an internal clock signal and a single pulse signal, respectively synchronized with an input clock signal; a plurality of delay units being connected in series with each other and configured to generate respective delayed clock signals; a plurality of latch circuits configured to latch the single pulse signal in synchronization with the respective delayed clock signals, and output sampling signals; and a count sub-circuit configured to output a count value resulting from counting a number of active sampling signals of the sampling signals.

Abstract: An oscillator control circuit includes a zero-temperature coefficient (ZTC) estimator estimating a ZTC voltage based on a supply voltage supplied to the oscillator and a frequency of an oscillation signal output by the oscillator. The ZTC voltage is the magnitude of the supply voltage VDD which corresponds to the ZTC condition for the oscillator. The ZTC estimator generates a bias control signal such that the magnitude of the supply voltage becomes the ZTC voltage.

Abstract: A touch screen panel includes a transparent substrate, a first sensing line and a second sensing line. The first sensing line includes first sensing cells arranged along a first direction and first connection patterns coupling the first sensing cells. The second sensing line includes second sensing cells arranged in a second direction substantially perpendicular to the first direction, and second connection patterns coupling the second sensing cells. At least one of the first and the second sensing cells includes openings and conductive patterns located in the openings.

Abstract: A current reference circuit includes a reference current supply unit configured to generate a reference current having a target current level, a current-frequency converter configured to receive a first temporary reference current corresponding to the reference current from the reference current supply unit and to generate a first comparison clock signal in response to the first temporary reference current, and a first current compensation unit configured to generate a first current compensation signal used for the first temporary reference current to reach the target current level in response to a frequency of a reference clock signal and a frequency of the first comparison clock signal.