Patents by Inventor Tae-wook Seo

Tae-wook Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240129211
    Abstract: An apparatus for predicting a traffic speed and a method thereof are provided. The apparatus includes an input device that receives traffic speed sequences of a plurality of links and a controller that detects a spatio-temporal relationship between traffic speeds of the plurality of links and predicts a future traffic speed of a target link based on the spatio-temporal relationship between the traffic speeds of the plurality of links.
    Type: Application
    Filed: March 6, 2023
    Publication date: April 18, 2024
    Inventors: Nam Hyuk Kim, Tae Heon Kim, Sung Hwan Park, Sang Wook Kim, Jun Ho Song, Ji Won Son, Dong Hyuk Seo
  • Publication number: 20240122048
    Abstract: A display device includes a light-emitting device disposed on a substrate and including an emission layer, and a light controller disposed on the light-emitting device. The light controller includes a plurality of main light blocking patterns extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, and a plurality of sub-light blocking patterns disposed between adjacent ones of the plurality of main light blocking patterns, extending in the first direction, and spaced apart from each other in the second direction. Each of the plurality of main light blocking patterns has a first thickness in a thickness direction of the substrate, and each of the plurality of sub-light blocking patterns has a second thickness that is less than the first thickness in the thickness direction of the substrate.
    Type: Application
    Filed: May 31, 2023
    Publication date: April 11, 2024
    Applicant: Samsung Display Co., LTD.
    Inventors: Kab Jong SEO, Tae Wook KANG, Jun Ho SIM, Jae Hun LEE, Yang-Ho JUNG
  • Patent number: 11942018
    Abstract: A display device is described including a display panel for displaying an image and an input sensing unit disposed on the display panel for sensing a user input. The input sensing unit includes: an electrode unit including first electrodes and second electrodes which intersect each other and a control unit for determining the proximity of an object or the shape of the object, based on capacitance change values of the first electrodes and the second electrodes. In a first mode the input sensing unit is driven using a self-capacitance method. The control unit may merge the capacitance change values, and determine the proximity of the object based on the merged value. In a second mode based on mutual capacitance, the control unit may determine the shape of the object.
    Type: Grant
    Filed: October 4, 2022
    Date of Patent: March 26, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jae Woo Choi, Tae Joon Kim, Eun Sol Seo, Hyun Wook Cho
  • Publication number: 20140373782
    Abstract: Provided is a substrate processing apparatus. The substrate processing apparatus includes a chamber in which a processing space is defined, a substrate support disposed in the chamber and supporting a substrate; and an upper electrode to which a radio frequency (RF) power is applied, the upper electrode facing the substrate support. The substrate support includes a plurality of ground electrodes spaced apart from each other and independently controlled so that plasma is uniformly generated to an edge area of the substrate support between the upper electrode and the substrate support. The substrate processing apparatus may uniformly control plasma distribution or density on a substrate and a periphery of the substrate and may uniformly control plasma distribution or density in the central area of the substrate and the edge area of the substrate.
    Type: Application
    Filed: June 20, 2014
    Publication date: December 25, 2014
    Inventors: Yong Gyun PARK, Tae Wook SEO, Nae Il LEE
  • Patent number: 8029859
    Abstract: There is provided a method of depositing a Ge—Sb—Te thin film, including: a Ge—Sb—Te thin-film forming step of feeding and purging a first precursor including any one of Ge, Sb and Te, a second precursor including another one of Ge, Sb and Te and a third precursor including the other one of Ge, Sb and Te into and from a chamber in which a wafer is mounted and forming the Ge—Sb—Te thin film on the wafer; and a reaction gas feeding step of feeding reaction gas while any one of the first to third precursors is fed.
    Type: Grant
    Filed: August 22, 2006
    Date of Patent: October 4, 2011
    Assignee: Integrated Process Systems Ltd.
    Inventors: Jung-Wook Lee, Byung-Chul Cho, Ki-Hoon Lee, Tae-Wook Seo
  • Patent number: 7842606
    Abstract: Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: November 30, 2010
    Assignee: Integrated Process Systems Ltd
    Inventors: Ki Hoon Lee, Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo, Ho Seung Chang
  • Patent number: 7785664
    Abstract: A method is provided for depositing thin films in which the thin films are continuously deposited into one chamber and 1-6 wafers are loaded into the chamber. In the method, a process gap between a shower head or a gas injection unit and a substrate is capable of being controlled. The method comprises (a) loading at least one substrate into the chamber, (b) depositing the Ti thin film onto the substrate, adjusted so that a first process gap is maintained, (c) moving a wafer block so that the first process gap is changed into a second process gap in order to control the process gap of the substrate upon which the Ti thin film is deposited, (d) depositing the TiN thin film onto the substrate, moved to set the second process gap, and (e) unloading the substrate upon which the Ti/TiN thin films are deposited.
    Type: Grant
    Filed: December 14, 2005
    Date of Patent: August 31, 2010
    Assignee: IPS Ltd.
    Inventors: Tae Wook Seo, Young Hoon Park, Ki Hoon Lee, Sahng Kyoo Lee
  • Patent number: 7638437
    Abstract: Provided is an in-situ thin-film deposition method in which a TiSix/Ti layer or TiSix/Ti/TiN layer can be continuously deposited. The method serves to deposit a thin layer as a resistive contact and barrier on a loaded wafer and is performed in a thin-film deposition apparatus including a transfer chamber having a robot arm therein and a plurality of chambers installed as a cluster type on the transfer chamber. The method includes depositing a TiSix layer on the wafer by supplying a first reactive gas containing Ti and a second reactive gas containing Si to a first chamber; and transferring the wafer to a second chamber using the transfer chamber and depositing a TiN layer on the TiSix layer.
    Type: Grant
    Filed: October 27, 2005
    Date of Patent: December 29, 2009
    Assignee: IPS Ltd.
    Inventors: Tae Wook Seo, Young Hoon Park
  • Publication number: 20080166887
    Abstract: Disclosed herein are a method of depositing a thin film and a method of manufacturing a semiconductor using the same, having high selectivity by increasing etching resistance while an extinction coefficient associated with anti-reflectivity is maintained low. The method of depositing a thin film according to the invention includes (a) depositing an carbon anti-reflective film on the bottom film of a substrate; and (b) adding a compound containing nitrogen (N), fluorine (F) or silicon (Si) to the surface or the inner portion of the carbon anti-reflective film, to deposit a thin film of a-C:N, a-C:F or a-C:Si, having high selectivity, to a thickness from 1 to 100 nm using an atomic layer deposition process. Therefore, an ultrathin film having etching resistance is formed on or in the carbon anti-reflective film and the density and compressive stress of the carbon anti-reflective film are increased, thus increasing etching selectivity.
    Type: Application
    Filed: November 28, 2005
    Publication date: July 10, 2008
    Applicant: INTEGRATED PROCESS SYSTEMS LTD
    Inventors: Ki Hoon Lee, Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo, Ho Seung Chang
  • Patent number: 7253101
    Abstract: Provided is a method of depositing a metal nitride film having a multilayer structure and different deposition speeds on a substrate. The method is performed by forming a first lower metal nitride film on the substrate at a first deposition speed, forming a second lower metal nitride film on the first lower metal nitride film at a second deposition speed, and forming an upper metal nitride film having a large content of nitrogen (N) on a lower TiN film which is formed by the forming of the first lower metal nitride film and the second lower metal nitride film, at a third deposition speed, to improve stability with respect to exposure to air/moisture. The deposition speed of the metal nitride film having a multi-layer structure satisfies a relationship that the second deposition speed?the first deposition speed?the third deposition speed.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: August 7, 2007
    Assignee: IPS Ltd.
    Inventors: Young Hoon Park, Sahng Kyoo Lee, Tae Wook Seo
  • Publication number: 20070144557
    Abstract: A dry cleaning method for an apparatus for depositing a thin film that deposits an Al-containing metal film and an Al-containing metal nitride film is provided. The method includes maintaining a temperature inside of chamber of the apparatus for depositing a thin film at 430° C. or higher and cleaning the inside of the chamber by supplying a cleaning gas including Cl2 into the chamber. When it is difficult to maintain the temperature inside the chamber at 430° C. or higher, the method includes cleaning the inside of the chamber by using a cleaning gas including Cl2 plasma. Accordingly, the apparatus for depositing the thin film that deposits a titanium aluminum nitride (TiAlN) film and a similar type thin film can be effectively cleaned without having remaining products and particles.
    Type: Application
    Filed: August 22, 2006
    Publication date: June 28, 2007
    Inventors: Ki-Hoon Lee, Sang-Jin Lee, Tae-Wook Seo
  • Publication number: 20070048977
    Abstract: There is provided a method of depositing a Ge—Sb—Te thin film, including: a Ge—Sb—Te thin-film forming step of feeding and purging a first precursor including any one of Ge, Sb and Te, a second precursor including another one of Ge, Sb and Te and a third precursor including the other one of Ge, Sb and Te into and from a chamber in which a wafer is mounted and forming the Ge—Sb—Te thin film on the wafer; and a reaction gas feeding step of feeding reaction gas while any one of the first to third precursors is fed.
    Type: Application
    Filed: August 22, 2006
    Publication date: March 1, 2007
    Inventors: Jung-Wook Lee, Byung-Chul Cho, Ki-Hoon Lee, Tae-Wook Seo
  • Publication number: 20030199146
    Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.
    Type: Application
    Filed: March 19, 2003
    Publication date: October 23, 2003
    Inventors: Jin-Ho Jeon, Byoung-Deog Choi, Jong-Seung Yi, Tae-Wook Seo
  • Patent number: 6569782
    Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.
    Type: Grant
    Filed: March 8, 2001
    Date of Patent: May 27, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Ho Jeon, Byoung-Deog Choi, Jong-Seung Yi, Tae-Wook Seo
  • Patent number: 6387776
    Abstract: A method for forming trench isolation regions in a semiconductor device reliably electrically isolates a device and enhances a device density. The method for forming trench isolation regions includes forming a trench on a surface of a semiconductor device with a predetermined depth; forming a nitride liner layer on the surface of the semiconductor including the trench, forming a gas distribution region which is uniformly distributed on the nitride liner layer; and forming an insulation layer by filling the trench after said forming of the gas distribution region. The gas distribution region is preferably formed by introducing an ozone gas. The insulation layer is preferably formed by simultaneously introducing ozone gas and TEOS(Tetra Ethyl Ortho-Silicate) chemical.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: May 14, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Seung Yi, Tae Wook Seo, Jin-Ho Jeon
  • Patent number: 6376303
    Abstract: A method of manufacturing a capacitor having a high storage capacitance and a method of fabricating semiconductor devices incorporating the same include measures to ensure that the substrate and/or components of the device are not thermally damaged during the process of forming a sacrificial structure of doped oxide layers used as a form in producing the storage electrode of the capacitor. The oxide layers are formed over the substrate by LPCVD or PECVD, which processes can be carried out at a temperature of only about 400-600° C. Each one of an adjacent pair of the doped oxide layers has a different etching rate from the other as the result of a difference (type or amount) in impurities contained in the oxide layers. At least one hole is formed in the sacrificial structure to create a side wall of the sacrificial structure. The side wall is etched so that repeating tooth-like prominences and depressions are formed at the side wall as the result of the different etching rates of the oxide layers.
    Type: Grant
    Filed: February 7, 2000
    Date of Patent: April 23, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae Wook Seo, Jeon Sig Lim
  • Patent number: 6372555
    Abstract: A novel fuse structure for a semiconductor integrated circuit device and the method of manufacturing the semiconductor integrated circuit device is disclosed. The fuse structure is comprised of a first interconnection metal layer formed on a semiconductor substrate; an inter-metal dielectric layer formed on the first interconnection metal layer having a via exposing the first interconnection metal layer; a via plug filling up the via; a metal layer for a fuse and a second interconnection metal layer consecutively deposited on the via plug and the inter-metal dielectric layer; and an opening area exposing the metal layer for a fuse is positioned more than twice the thickness of the second interconnection metal layer from the via. With the present invention, a contact failure which can result from a damage to via plug in a subsequent stripping step can be prevented.
    Type: Grant
    Filed: September 21, 1999
    Date of Patent: April 16, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Jae Lee, Tae-Wook Seo, Sun-Hoo Park
  • Publication number: 20020000644
    Abstract: An insulating layer having a BPSG layer, a semiconductor device and methods for fabricating them. After preparing an oxidizing atmosphere using an oxygen gas, a first seed layer is formed with a tetraethylorthosilicate (TEOS) and the oxygen gas. Thereafter, a second seed layer, used to form an insulating layer capable of controlling an amount of a boron, is formed by means of using a triethylborate (TEB), the TEOS and the oxygen gas. Then, the insulating layer having a BPSG layer is formed using the TEB, a triethylphosphate, the TEOS and an ozone gas. About 5.25 to 5.75% by weight of the boron and about 2.75 to 4.25% by weight of the phosphorous are added to the insulating layer.
    Type: Application
    Filed: March 8, 2001
    Publication date: January 3, 2002
    Inventors: Jin-Ho Jeon, Byoung-Deog Choi, Jong-Seung Yi, Tae-Wook Seo
  • Patent number: 6329276
    Abstract: There is provided a semiconductor device fabrication method. In the method, a gate layer is formed on a semiconductor substrate and patterned to form a first resultant structure, a metal layer is formed on the first resultant structure, a capping layer is formed on the metal layer, a metal silicide is formed on the gate layer by heating the substrate at a first temperature, unreacted metal layer and first capping layer are removed to form a second resultant structure, a second capping layer is formed on the second resultant structure, and the substrate is heated at a second temperature higher than the first temperature. The second capping layer suppresses a silicidation rate in the secondary heat treatment, thereby allowing a silicide of a good morphology to be achieved.
    Type: Grant
    Filed: September 9, 1999
    Date of Patent: December 11, 2001
    Assignee: Samsung Electronics Co. Ltd.
    Inventors: Ja-Hum Ku, Soo-Geun Lee, Chul-Sung Kim, Tae-Wook Seo, Eung-Joon Lee, Joo-Hyuk Chung
  • Patent number: 6291342
    Abstract: A method of forming a multilayer titanium nitride film hardly containing any Cl component by a multiple step chemical vapor deposition method, and a method of manufacturing a semiconductor device using the same are provided. In the present invention, a multilayer TiN film is formed by multiple step chemical vapor deposition (CVD) on a semiconductor substrate on which an underlayer is formed. In order to form the multilayer TiN film, an underlayer protective TiN film is formed by forming a first TiN film on the underlayer and NH3 annealing the first TiN film. A main TiN film is formed by forming a second TiN film on the underlayer protective TiN film and NH3 annealing the second TiN film. A source gas used in order to form the first TiN film has a smaller TiCl4 to NH3 gas flow ratio than a source gas for forming the second TiN film. In order to apply the multilayer TiN film to the fabrication of the semiconductor device, an insulating film having a contact hole is formed on a semiconductor substrate.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: September 18, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jang-eun Lee, Ju-hyuck Chung, Tae-wook Seo