Patents by Inventor Tae-Yeol Kim
Tae-Yeol Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11953211Abstract: A method and an apparatus for real-time analysis of the district heating network is disclosed. According to an embodiment of the present disclosure, a method for analyzing a district heating network including pipes and fluids inside the pipes includes receiving, by a processor, pipe data representing a structure of the pipes; receiving, by the processor, input data on at least one of the physical state of the district heating network and the flow of fluids; calculating, by the processor, data for at least one of the physical state of the district heating network or the flow of fluids using the pipe data and the input data.Type: GrantFiled: January 20, 2023Date of Patent: April 9, 2024Assignee: GS Power Co. Ltd.Inventors: Yuan Hu Li, Chang Yeol Yoon, Ki Song Lee, Kun Young Lee, Tae Gon Kim
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Publication number: 20240077660Abstract: The present invention provides an optical filter having a narrow bandpass, high transmittance in the bandpass, low transmittance outside the bandpass, little change in optical properties even when the incident angle of light changes and thus, being advantageous in terms of yield and cost per hour. In addition, the present invention may provide a LiDAR system including the optical filter and an application of the optical filter and the LiDAR system.Type: ApplicationFiled: June 1, 2023Publication date: March 7, 2024Inventors: Jung Yeol SHIN, Tae Jin SONG, Seong Yong YOON, Jin Hwan KIM
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Patent number: 11923426Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.Type: GrantFiled: July 6, 2021Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Won Kang, Tae-Yeol Kim, Jeong Ik Kim, Rak Hwan Kim, Jun Ki Park, Chung Hwan Shin
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Publication number: 20240014250Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: ApplicationFiled: September 21, 2023Publication date: January 11, 2024Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
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Patent number: 11869836Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: GrantFiled: February 6, 2023Date of Patent: January 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghee Seo, Heonbok Lee, Tae-Yeol Kim, Daeyong Kim, Dohyun Lee
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Patent number: 11804516Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: GrantFiled: December 10, 2020Date of Patent: October 31, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
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Publication number: 20230187335Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Inventors: Donghee SEO, Heonbok LEE, Tae-Yeol KIM, Daeyong KIM, Dohyun LEE
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Patent number: 11596659Abstract: A composition for preventing or treating an infection or disease caused by a pathogenic Escherichia coli includes a Myoviridae bacteriophage Esc-COP-18 having an ability to lyse the pathogenic Escherichia coli and a pharmaceutically acceptable carrier. A method for preventing or treating an infection or disease caused by a pathogenic Escherichia coli includes administering to a subject a Myoviridae bacteriophage and lysing the pathogenic Escherichia coli by the Myoviridae bacteriophage.Type: GrantFiled: May 12, 2020Date of Patent: March 7, 2023Assignee: iNtRON Biotechnology, Inc.Inventors: Seong Jun Yoon, Jee Soo Son, In Hwang Kim, Hyoung Rok Paik, Hyun Joo Im, Hyun Jin Yu, Cheol Ahn, Tae Yeol Kim, Soo Youn Jun, Sang Hyeon Kang
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Patent number: 11581253Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: GrantFiled: October 18, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghee Seo, Heonbok Lee, Tae-Yeol Kim, Daeyong Kim, Dohyun Lee
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Publication number: 20230011401Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: ApplicationFiled: September 16, 2022Publication date: January 12, 2023Inventors: Hyun-Seung Song, Tae-Yeol Kim, Jae-Jik Baek
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Patent number: 11482602Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: GrantFiled: September 28, 2020Date of Patent: October 25, 2022Inventors: Hyun-Seung Song, Tae-Yeol Kim, Jae-Jik Baek
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Publication number: 20220130970Abstract: A semiconductor device capable of improving a device performance and a reliability is provided. The semiconductor device comprising a gate structure including a gate electrode on a substrate, a source/drain pattern on a side face of the gate electrode, on the substrate and, a source/drain contact connected to the source/drain pattern, on the source/drain pattern, a gate contact connected to the gate electrode, on the gate electrode, and a wiring structure connected to the source/drain contact and the gate contact, on the source/drain contact and the gate contact, wherein the wiring structure includes a first via plug, a second via plug, and a wiring line connected to the first via plug and the second via plug, the first via plug has a single conductive film structure, and the second via plug includes a lower via filling film, and an upper via filling film on the lower via filling film.Type: ApplicationFiled: July 6, 2021Publication date: April 28, 2022Inventors: Ji Won KANG, Tae-Yeol KIM, Jeong Ik KIM, Rak Hwan KIM, Jun Ki PARK, Chung Hwan SHIN
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Publication number: 20220044993Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: ApplicationFiled: October 18, 2021Publication date: February 10, 2022Inventors: Donghee SEO, Heonbok LEE, Tae-Yeol KIM, Daeyong KIM, Dohyun LEE
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Publication number: 20210353695Abstract: A composition for preventing or treating an infection or disease caused by a pathogenic Escherichia coli includes a Myoviridae bacteriophage (Esc-COP-18) having an ability to lyse the pathogenic Escherichia coli and a pharmaceutically acceptable carrier. A method for preventing or treating an infection or disease caused by a pathogenic Escherichia coli includes administering to a subject a Myoviridae bacteriophage and lysing the pathogenic Escherichia coli by the Myoviridae bacteriophage.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Inventors: Seong Jun YOON, Jee Soo SON, In Hwang KIM, Hyoung Rok PAIK, Hyun Joo IM, Hyun Jin YU, Cheol AHN, Tae Yeol KIM, Soo Youn JUN, Sang Hyeon KANG
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Patent number: 11152297Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: GrantFiled: June 5, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Donghee Seo, Heonbok Lee, Tae-Yeol Kim, Daeyong Kim, Dohyun Lee
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Publication number: 20210217861Abstract: A semiconductor device is disclosed. The semiconductor device includes a gate electrode on a substrate and extending in a first direction, source/drain patterns spaced apart from each other, in a second direction, with the gate electrode interposed therebetween, a gate contact electrically connected to the gate electrode, and an active contact electrically connected to at least one of the source/drain patterns. The active contact includes a lower contact pattern electrically connected to the at least one of the source/drain patterns, the lower contact pattern having a first width in the first direction, and an upper contact pattern electrically connected to a top surface of the lower contact pattern, the upper contact pattern having a second width in the first direction that is smaller than the first width. The upper contact pattern and the gate contact horizontally overlap each other.Type: ApplicationFiled: September 28, 2020Publication date: July 15, 2021Inventors: HYUN-SEUNG SONG, Tae-Yeol Kim, Jae-Jik Baek
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Publication number: 20210167004Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.Type: ApplicationFiled: June 5, 2020Publication date: June 3, 2021Inventors: Donghee SEO, Heonbok LEE, Tae-Yeol KIM, Daeyong KIM, Dohyun LEE
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Publication number: 20210098563Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: ApplicationFiled: December 10, 2020Publication date: April 1, 2021Inventors: Tae-yeol KIM, Hyon-wook RA, Seo-bum LEE, Jun-soo KIM, Chung-hwan SHIN
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Patent number: 10886361Abstract: A semiconductor device is provided including a resistor structure, the semiconductor device including a substrate having an upper surface perpendicular to a first direction; a resistor structure including a first insulating layer on the substrate, a resistor layer on the first insulating layer, and a second insulating layer on the resistor layer; and a resistor contact penetrating the second insulating layer and the resistor layer. The tilt angle of a side wall of the resistor contact with respect to the first direction varies according to a height from the substrate. The semiconductor device has a low contact resistance and a narrow variation of contact resistance.Type: GrantFiled: January 5, 2018Date of Patent: January 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Tae-yeol Kim, Hyon-wook Ra, Seo-bum Lee, Jun-soo Kim, Chung-hwan Shin
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Patent number: 10847464Abstract: A semiconductor device and a method of forming the same, the semiconductor device including an insulating structure having an opening; a conductive pattern disposed in the opening; a barrier structure covering a bottom surface of the conductive pattern, the barrier structure extending between the conductive pattern and side walls of the opening; and a nucleation structure disposed between the conductive pattern and the barrier structure. The nucleation structure includes a first nucleation layer that contacts the barrier structure, and a second nucleation layer that contacts the conductive pattern, and a top end portion of the second nucleation layer is higher than a top end portion of the first nucleation layer.Type: GrantFiled: January 9, 2020Date of Patent: November 24, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Tae Yeol Kim, Ji Won Kang, Chung Hwan Shin, Jin Il Lee, Sang Jin Hyun