Patents by Inventor Tae Yoshikawa
Tae Yoshikawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7142276Abstract: The TFT substrate of an LCD device has an array of pixel electrodes defined by a plurality of signal lines and a plurality of scanning lines. Each terminal of the scanning lines includes a first metallic pattern, a second metallic pattern in contact with the first metallic pattern through a first via hole, and an ITO pattern in contact with the second metallic pattern through a second via hole. The ITO pattern has a width smaller than the width of the first via hole and larger than the second via hole, thereby providing the TFT substrate with a smaller level difference. The smaller level difference prevents the dust generated during a rubbing treatment from attaching onto the TFT substrate.Type: GrantFiled: May 19, 2004Date of Patent: November 28, 2006Assignee: NEC LCD Technologies, Ltd.Inventor: Tae Yoshikawa
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Patent number: 6891196Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode is isolated in each layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer and a TFF area. A drain electrode layer is formed by a first passivation film with the first passivation film formed as an upper layer. In a second passivation film, formed above the first passivation film, are bored a first opening through the first and second passivation films and a second opening through the second passivation film. A wiring connection layer is formed by ITO provided as an uppermost layer.Type: GrantFiled: July 11, 2003Date of Patent: May 10, 2005Assignee: NEC LCD Technologies, Ltd.Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
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Patent number: 6890783Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: GrantFiled: September 12, 2002Date of Patent: May 10, 2005Assignee: NEC LCD Technologies, LTD.Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20040239857Abstract: The TFT substrate of an LCD device has an array of pixel electrodes defined by a plurality of signal lines and a plurality of scanning lines. Each terminal of the scanning lines includes a first metallic pattern, a second metallic pattern in contact with the first metallic pattern through a first via hole, and an ITO pattern in contact with the second metallic pattern through a second via hole. The ITO pattern has a width smaller than the width of the first via hole and larger than the second via hole, thereby providing the TFT substrate with a smaller level difference. The smaller level difference prevents the dust generated during a rubbing treatment from attaching onto the TFT substrate.Type: ApplicationFiled: May 19, 2004Publication date: December 2, 2004Applicant: NEC LCD Technologies, Ltd.Inventor: Tae Yoshikawa
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Publication number: 20040084672Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer.Type: ApplicationFiled: July 11, 2003Publication date: May 6, 2004Applicant: NEC LCD Technologies, Ltd.Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
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Patent number: 6674093Abstract: An active matrix substrate of a channel protection type having a gate electrode, a drain electrode and a pixel electrode isolated from one another from layer to layer by insulating films. The active matrix substrate is to be prepared by four masks. A gate electrode layer, a gate insulating film and an a-Si layer are processed to the same shape on a transparent insulating substrate to form a gate electrode layer (102 of FIG. 6) and a TFF area. A drain electrode layer (106 of FIG. 6) is formed by a first passivation film (105 of FIG. 6) via a first passivation film (105 of FIG. 6) formed as an upper layer. In a second passivation film (107 of FIG. 6) formed above it are bored an opening through the first and second passivation films and an opening through the second passivation film. A wiring connection layer is formed by ITO (108 of FIG. 6) provided as an uppermost layer.Type: GrantFiled: October 25, 2000Date of Patent: January 6, 2004Assignee: NEC LCD Technologies, Ltd.Inventors: Hiroaki Tanaka, Hirotaka Yamaguchi, Wakahiko Kaneko, Michiaki Sakamoto, Satoshi Ihida, Takasuke Hayase, Tae Yoshikawa, Hiroshi Kanou
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Patent number: 6632696Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: GrantFiled: December 20, 2000Date of Patent: October 14, 2003Assignee: NEC CorporationInventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20030013221Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: ApplicationFiled: September 12, 2002Publication date: January 16, 2003Inventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi
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Publication number: 20010010370Abstract: An active matrix substrate plate having superior properties is manufactured at high yield using four photolithographic fabrication steps. In step 1, the scanning line and the gate electrode extending from the scanning line are formed in the glass plate. In step 2, the gate insulation layer and the semiconductor layer comprised by amorphous silicon layer and n+ amorphous silicon layer is laminated to provide the semiconductor layer for the TFT section. In step 3, the transparent conductive layer and the metallic layer are laminated, and the signal line, the drain electrode extending from the signal line, the pixel electrode and the source electrode extending from the pixel electrode are formed, and the n+ amorphous silicon layer of the channel gap is removed by etching. In step 4, the protective insulation layer is formed, and the protective insulation layer and the metal layer above the pixel electrode are removed by etching.Type: ApplicationFiled: December 20, 2000Publication date: August 2, 2001Applicant: NEC CorporationInventors: Shigeru Kimura, Takahiko Watanabe, Tae Yoshikawa, Hiroyuki Uchida, Shusaku Kido, Shinichi Nakata, Tsutomu Hamada, Hisanobu Shimodouzono, Satoshi Doi, Toshihiko Harano, Akitoshi Maeda, Satoshi Ihida, Hiroaki Tanaka, Takasuke Hayase, Shouichi Kuroha, Hirofumi Ihara, Kazushige Takechi