Abstract: A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.

Abstract: A power semiconductor device includes a substrate, including an active region and edge regions, including a semiconductor layer of a first conductive type including silicon carbide (SiC); an insulating film disposed on the edge regions; a field plate pattern disposed on the insulating film; a first doped region of a second conductive type disposed inside the substrate to extend downward from a top surface of the edge regions; a second doped region of the second conductive type, buried in the edge regions, extends in a direction having a vector component parallel to the top surface of the substrate; and a third doped region of the first conductive type is disposed on the second doped region and at a side portion of the first doped region.

Abstract: A power semiconductor device according to an aspect of the present disclosure includes a semiconductor layer of silicon carbide (SiC), a plurality of well regions that is disposed in the semiconductor layer, spaced from each other and has a second conductivity type, a plurality of source regions that are disposed in the semiconductor layer on the plurality of well regions respectively, spaced from each other, a drift region that has the first conductivity type and is disposed in the semiconductor layer, the drift region extending from a lower side of the plurality of well regions to a surface of the semiconductor layer through between the plurality of well regions, a plurality of trenches, a gate insulating layer, and a gate electrode layer that is disposed on the gate insulating layer.

Abstract: A power semiconductor device includes a semiconductor layer of silicon carbide (SiC), at least one trench that extends in one direction, a gate insulating layer disposed on at least an inner wall of the at least one trench, at least one gate electrode layer disposed on the gate insulating layer, a drift region disposed in the semiconductor layer at least on one side of the at least one gate electrode layer, a well region disposed in the semiconductor layer to be deeper than the at least one gate electrode layer, a source region disposed in the well region, and at least one channel region disposed in the semiconductor layer of one side of the at least one gate electrode layer between the drift region and the source region.

Abstract: A power semiconductor device includes a semiconductor layer of SiC, a gate insulating layer, a gate electrode layer, a drift region including at least one protruding portion in the semiconductor layer and having a first conductivity type, a well region including a first well region in the semiconductor layer and in contact with the protruding portion, and a second well region in the semiconductor layer outside the gate electrode layer and connected to the first well region, and having a second conductivity type, a source region including a first source region in the first well region and a second source region in the second well region and connected to the first source region, and having the first conductivity type, and a channel region under the gate electrode layer, in the semiconductor layer between the protruding portion and the first source region, and having the first conductivity type.

Abstract: The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.

Abstract: The power semiconductor device includes: a first trench gate and a second trench gate in a stripe shape extending in one direction in parallel and spaced apart from each other in a substrate; a third trench gate in a ladder shape extending in a direction different from the one direction between the first trench gate and the second trench gate in the substrate; a first conductive type body area each disposed between the first trench gate, the second trench gate and the third trench gate, respectively, in the substrate; a pair of first conductive type floating first areas surrounding each of bottom surfaces and at least one side of the first trench gate and the second trench gate in the substrate; and a first conductive type floating second area surrounding a bottom surface of the third trench gate in the substrate.

Abstract: Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to bc separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type.

Abstract: Provided are a semiconductor device, the semiconductor device comprise, a substrate which comprises a first surface and a second surface facing the first surface, an epitaxial layer which is formed on the first surface of the substrate and has a first conductivity type, a base region which is formed in the epitaxial layer and has a second conductivity type different from the first conductivity type, a source region which is formed in the base region and has the first conductivity type, a channel region which is formed in the base region to be separated from the source region and has the first conductivity type and a barrier region which is formed between the source region and the channel region and has the second conductivity type