Patents by Inventor Taejin Yim

Taejin Yim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446495
    Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yoonhee Kang, Jiyoung Kim, Taejin Yim, Jongmin Baek, Sanghoon Ahn, Hyeoksang Oh, Kyu-Hee Han
  • Publication number: 20190043809
    Abstract: Embodiments of the present inventive concepts provide methods of forming an ultra-low-k dielectric layer and the ultra-low-k dielectric layer formed thereby. The method may include forming a first layer by supplying a precursor including silicon, oxygen, carbon, and hydrogen, performing a first ultraviolet process on the first layer to convert the first layer into a second layer, and performing a second ultraviolet process on the second layer under a process condition different from that of the first ultraviolet process.
    Type: Application
    Filed: March 1, 2018
    Publication date: February 7, 2019
    Inventors: Yoonhee KANG, Jiyoung Kim, Taejin Yim, Jongmin Baek, Sanghoon Ahn, Hyeoksang Oh, Kyu-Hee Han
  • Patent number: 10199325
    Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: February 5, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Taejin Yim, Jongmin Baek, Deokyoung Jung, Kyuhee Han, Byunghee Kim, Jiyoung Kim, Naein Lee, Sangshin Jang
  • Publication number: 20180151490
    Abstract: A semiconductor device is provided. The semiconductor device includes first metal lines on a lower layer, a dielectric barrier layer provided on the lower layer to cover side and top surfaces of the first metal lines, an etch stop layer provided on the dielectric barrier layer to define gap regions between the first metal lines, an upper insulating layer on the etch stop layer, and a conductive via penetrating the upper insulating layer, the etch stop layer, and the dielectric barrier layer to contact a top surface of a first metal line. The etch stop layer includes first portions on the first metal lines and second portions between the first metal lines. The second portions of the etch stop layer are higher than the first portions.
    Type: Application
    Filed: October 25, 2017
    Publication date: May 31, 2018
    Inventors: Taejin YIM, Jongmin BAEK, Deokyoung JUNG, Kyuhee HAN, Byunghee KIM, Jiyoung KIM, Naein LEE, Sangshin JANG
  • Patent number: 9576848
    Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: February 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Taejin Yim, Thomas Oszinda, Byunghee Kim, Sanghoon Ahn, Naein Lee, Keeyoung Jun
  • Publication number: 20160148837
    Abstract: A method of treating a porous dielectric layer includes preparing a substrate on which the porous dielectric layer including an opening and pores exposed by the opening is formed, supplying a first precursor onto the substrate to form a first sub-sealing layer sealing the exposed pores, and supplying a second precursor onto the first sub-sealing layer to form a second sub-sealing layer covering the first sub-sealing layer. Each of the first and second precursors includes silicon, and a molecular weight of the second precursor is smaller than that of the first precursor.
    Type: Application
    Filed: September 8, 2015
    Publication date: May 26, 2016
    Inventors: Taejin Yim, Thomas Oszinda, Byunghee Kim, Sanghoon Ahn, Naein Lee, Keeyoung Jun
  • Patent number: 9312171
    Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 12, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyu-Hee Han, Pil-Kyu Kang, Taejin Yim, Naein Lee
  • Publication number: 20150155233
    Abstract: The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.
    Type: Application
    Filed: September 19, 2014
    Publication date: June 4, 2015
    Inventors: Kyu-Hee Han, Pil-Kyu Kang, Taejin Yim, Naein Lee