Abstract: Integrated circuit structures having backside self-aligned conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and is on and in contact with the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

Abstract: Integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, and methods of fabricating integrated circuit structures having backside self-aligned penetrating conductive source or drain contacts, are described. For example, an integrated circuit structure includes a sub-fin structure over a vertical stack of horizontal nanowires. An epitaxial source or drain structure is laterally adjacent and coupled to the vertical stack of horizontal nanowires. A conductive source or drain contact is laterally adjacent to the sub-fin structure and extends into the epitaxial source or drain structure. The conductive source or drain contact does not extend around the epitaxial source or drain structure.

Abstract: The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Reducing transistor dimensions at the gate allows keeping the footprint of the transistor relatively small and comparable to what could be achieved implementing a transistor with a shorter gate length while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower.

Abstract: Gate-all-around integrated circuit structures having common metal gates and having gate dielectrics with differentiated dipole layers are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a mid-gap to P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a first dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having the mid-gap to P-type conductive layer over a second gate dielectric including the high-k dielectric layer and a second dipole material layer, the second dipole layer different than the first dipole material layer.

Abstract: Spacer self-aligned via structures for gate contact or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate. A plurality of conductive trench contact structures is alternating with the plurality of gate structures. A corresponding one of a plurality of dielectric spacers is between adjacent ones of the plurality of gate structures and the plurality of conductive trench contact structures. The plurality of dielectric spacers protrudes above the plurality of gate structures and above the plurality of conductive trench contact structures. A conductive structure is in direct contact with one of the plurality of gate structures or with one of the plurality of conductive trench contact structures. The conductive structure has a flat edge along a direction across the one of the plurality of gate structures or the one of the plurality of conductive trench contact structures.

Abstract: Gate-all-around integrated circuit structures having additive gate structures are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric, and an intervening conductive seed layer between the P-type conductive layer and the first gate dielectric. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric, and the intervening conductive seed layer between the N-type conductive layer and the second gate dielectric. The P-type gate stack is in contact with the N-type gate stack.

Abstract: Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

Abstract: Gate-all-around integrated circuit structures having dual metal gates and gate dielectrics with a single polarity dipole layer are described. For example, an integrated circuit structure includes a first vertical arrangement of horizontal nanowires, and a second vertical arrangement of horizontal nanowires. A P-type gate stack is over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric including a high-k dielectric layer and a dipole material layer. An N-type gate stack is over the second vertical arrangement of horizontal nanowires, the N-type gate stack having a mid-gap conductive layer over a second gate dielectric including the high-k dielectric layer and the dipole material layer.

Abstract: Epitaxial oxide plugs are described for imposing strain on a channel region of a proximate channel region of a transistor. The oxide plugs form epitaxial and coherent contact with one or more source and drain regions adjacent to the strained channel region. The epitaxial oxide plugs can be used to either impart strain to an otherwise unstrained channel region (e.g., for a semiconductor body that is unstrained relative to an underlying buffer layer), or to restore, maintain, or increase strain within a channel region of a previously strained semiconductor body. The epitaxial crystalline oxide plugs have a perovskite crystal structure in some embodiments.

Abstract: Described herein are embedded dynamic random-access memory (eDRAM) memory cells and arrays, as well as corresponding methods and devices. An exemplary eDRAM memory array implements a memory cell that uses a thin-film transistor (TFT) as a selector transistor. One source/drain (S/D) electrode of the TFT is coupled to a capacitor for storing a memory state of the cell, while the other S/D electrode is coupled to a bitline. The bitline may be a shallow bitline in that a thickness of the bitline may be smaller than a thickness of one or more metal interconnects provided in the same metal layer as the bitline but used for providing electrical connectivity for components outside of the memory array. Such a bitline may be formed in a separate process than said one or more metal interconnects. In an embodiment, the memory cells may be formed in a back end of line process.

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract: Techniques are disclosed for forming transistors including source and drain (S/D) regions employing double-charge dopants. As can be understood based on this disclosure, the use of double-charge dopants for group IV semiconductor material (e.g., Si, Ge, SiGe) either alone or in combination with single-charge dopants (e.g., P, As, B) can decrease the energy barrier at the semiconductor/metal interface between the source and drain regions (semiconductor) and their respective contacts (metal), thereby improving (by reducing) contact resistance at the S/D locations. In some cases, the double-charge dopants may be provided in a top or cap S/D portion of a given S/D region, for example, so that the double-charge doped S/D material is located at the interface of that S/D region and the corresponding contact. The double-charge dopants can include sulfur (S), selenium (Se), and/or tellurium (Te). Other suitable group IV material double-charge dopants will be apparent in light of this disclosure.

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

Abstract: An integrated circuit device includes a device layer comprising a plurality of transistor devices, and an interconnect layer above the device layer. The interconnect layer includes a conductive interconnect feature. In an example, the interconnect feature includes (i) a bottom portion having a first diameter, and (ii) a top portion above the bottom portion. In an example, the top portion has a second diameter that is less than the first diameter by at least 10%. In an example, the interconnect feature includes a monolithic body of conductive material that is within both the top portion and the bottom portion.

Abstract: An integrated circuit device includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess. In an example, a top surface of the first interconnect feature is at least 1 nanometer (nm), or at least 3 nm, or at least 5 nm below a top surface of the first dielectric material. The second interconnect layer includes (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material. In an example, the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature. In an example, a bottom section of the second interconnect feature is within a top section of the recess.

Abstract: Techniques are provided herein to form fin cut structures, or fin isolation structures, after the metal gate has been formed. In an example, a row of semiconductor devices each include a semiconductor region extending in a first direction between a source region and a drain region, and a gate structure extending in a second direction over the semiconductor regions of each neighboring semiconductor device along the row. A fin cut structure that includes a dielectric material interrupts the gate structure and replaces the semiconductor region of one of the semiconductor devices, effectively cutting through the length of the semiconductor device fin (or nanoribbons). The gate structure is formed first followed by removing a portion of the gate structure and removing the semiconductor region of one of the semiconductor devices to form the fin cut structure. In this way, the fin cut structure does not interfere when forming the gate structure.

Abstract: An integrated circuit includes (i) a first transistor device having a first source or drain region coupled to a first source or drain contact, and a first gate electrode, (ii) a second transistor device having a second source or drain region coupled to a second source or drain contact, and a second gate electrode, (iii) a first dielectric material above the first and second source or drain contacts, (iv) a second dielectric material above the first and second gate electrodes, (v) a third dielectric material above the first and second dielectric materials, and (vi) an interconnect feature above and conductively coupled to the first source or drain contact. In an example, the interconnect feature comprises an upper body of conductive material extending within the third dielectric material, and a lower body of conductive material extending within the first dielectric material, with an interface between the upper and lower bodies.

Abstract: Techniques are provided herein to form semiconductor devices that use uniform topside dielectric plugs as masking structures to form conductive contacts to various source or drain regions. In an example, a plurality of semiconductor devices each include one or more semiconductor regions extending in a first direction between corresponding source or drain regions. The source or drain regions are adjacent to one another along a second direction different from the first direction. Conductive contacts are formed over the source or drain regions of the semiconductor devices. A dielectric fill is between one or more adjacent pairs of conductive contacts and dielectric masking structures having a substantially uniform thickness are present over the dielectric fill between adjacent pairs of conductive contacts. This uniform thickness characteristic applies to all of the masking structures regardless of their length along the second direction.

Abstract: Techniques are provided herein to form semiconductor devices having self-aligned gate cut structures. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut structure that includes a dielectric material interrupts the gate structure between the neighboring semiconductor devices. Due to the process of forming the gate cut structure, the distance between the gate cut structure and the semiconductor region of one of the neighboring semiconductor devices is substantially the same as (e.g., within 1.5 nm of) the distance between the gate cut structure and the semiconductor region of the other one of the neighboring semiconductor devices and the gate cut structure extends beyond the width of the gate structure to also interrupt gate spacers on the sidewalls of the gate structure.

Abstract: Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.