Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. The PGK circuits, group circuits, and carry circuits may use CMOS transmission gates in lieu of conventional complementary pass-gate logic (CPL).

Abstract: An encoding element (109, 111, 113) and a decoding arrangement (110, 112, 114) is included with each separate circuit (104, 105, 106) in a system (100) of circuits which must communicate digital signals with each other. The encoding devices (109, 111, 113) included with the separate circuits (104, 105, 106) cooperate to produce an encoded signal on a common transmission line or network (108) which interconnects the various circuits. The decoding arrangement (110, 112, 114) associated with each respective circuit receives the encoded signal appearing on the transmission line and decodes the encoded signal to reproduce or recreate the digital data signals transmitted from the other circuits in the system.

Abstract: For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.

Abstract: A memory array includes a storage unit with a number of sections and decoders coupled to respective ones of the sections for decoding an N-bit address signal and responsively asserting a signal on one of the word lines selected by the address signal. Local clock buffers are coupled to respective ones of the decoders for receiving a clock signal and an address signal including M most-significant bits of the N-bit address signal and generating respective timing signals. The decoders receive the timing signal from their respective local clock buffers. Each decoder is operable to alternately precharge and evaluate the N-bit address signal responsive to phases of the timing signal. Each local clock buffer is operable, responsive to a state of the M bits of the address signal, for selecting between holding its timing signal in a deasserted state and enabling its timing signal to follow the clock signal.

Abstract: An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is on at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry_ signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry_ signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Abstract: Digital signals from a group of three or more circuits (104, 105, 106) are used to create an encoded or combined signal on a common transmission line (108). The encoded signal is then decoded at each different circuit to produce or recreate the digital signal asserted by each different circuit in the group. The encoded signal comprises a signal included in a set of unique signal values, with each signal in the set corresponding to a different combination of digital signals asserted by the group of circuits. Decoding the encoded signal at each circuit (104, 105, 106) in the group involves comparing the encoded signal to a particular reference voltage from a set of reference voltages. A particular reference voltage used in this comparison may be selected using one or more digital signals already decoded from the encoded signal.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as program “states” with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process. If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: An adder circuit for determining the sum of two operands including a set of PGK circuits, at least one tier of group circuits, and a carry generation circuit. The PGK circuits are configured to generate propagate, generate, and kill bits corresponding to at least a portion of the first and second operands. The group circuit receives propagate, generate, and kill bits from a plurality of the PGK circuits and produces a set of group propagate, generate, and kill values. The carry generation circuit receives a carry-in bit and the outputs of at least one of the group circuits and generates a carry-out bit representing the carry-out of the corresponding group. Each generate bit is the logical AND of its corresponding bits in the first and second operand while each propagate bit is the EXOR of its corresponding bits, and each kill bit is the logical NOR of its corresponding bits.

Abstract: A compressor circuit suitable for use in an arithmetic unit of a microprocessor includes a first stage, a second stage, a carry circuit, and a sum circuit. The first stage is configured to receive a set of four input signals. The first stage generates a first intermediate signal indicative of the XNOR of a first pair of the input signals and a second intermediate signal indicative of the XNOR of a second pair of the input signals. The second stage configured to receive at least a portion of the signals generated by the first stage. The second stage generates first and second control signals where the first control signal is indicative of the XNOR of the four input signals and the second control signal is the logical complement of the first signal. The carry circuit is configured to receive at least one of the control signals and further configured to generate a carry bit based at least in part on the state of the received control signal.

Abstract: A method and system for authorizing access to networked information using a graphically based password. In one embodiment, access to a restricted document is granted only after the user has demonstrated its authority to access the information by identifying a previously determined sequence of graphical images. If the user identifies the correct images, the user is granted access to the restricted information. In one embodiment, the graphical images may be presented to the user as a sequence of web pages where each page has multiple graphical images (icons). On each page in the sequence, the user selects (such as by clicking) the correct icon. The icon may be implemented as a link to the next web page in the password sequence. As each page is presented, the user clicks the correct icon thereby generating a sequence of accessed web pages. The server then verifies the user as an authorized user by comparing the sequence of web pages visited by the user to a predetermined sequence.

Abstract: A mechanism is provided for highlighting items of interest in a set of web pages. The link highlighting mechanism may retrieve and examine web pages referenced by the instant web page. In this manner, the link highlighting mechanism may crawl through a set of web pages and highlight links that direct the user to the item of interest. The link highlighting mechanism may also record a user's click sequence to determine the most recently or most frequently visited links. The mechanism may then highlight the most recently or most frequently visited links to allow easy and quick navigation to items that are of particular interest to the user. The user may also enter properties of an item of interest, such as a file type or link type. The link highlighting mechanism examines a web page for items and links that match the property. If the user is using a mobile computing device or is otherwise operating with limited bandwidth, the highlighting mechanism may reside on a server.

Abstract: A server system and method in which the server determines whether a requesting client is accessing a requested document or page in a manner contemplated by the server. The server may first determine whether the client has direct access authority such as by interpreting cookie information supplied with the client request. The client may obtain direct access authority if the client has previously accessed server documents in a prescribed manner. If the client lacks direct access, the server may determine if the client has been referred or quoted to the requested page by a third party server or referrer that has authority to refer clients to the requested page. The server device may maintain a table of information in its storage to facilitate the determination of which referring parties have authority to which documents on the server.

Abstract: An adder circuit is provided that generates the sum and sum complement (sum_) signals by constructing the logic in such a way that various levels of both N-type devices and P-type devices are both “on” at the same when that leg is to be open. The logic is then determined by another level and only one P or N type device is one at a given time. For carry and carry complement (carry_) signals a circuit is provided that is symmetrical with respect to P and N devices. The carry and carry— signals are generated by inputting the complement signals to the same circuit used to generate the carry signal. The symmetrical P and N type devices are complementary in that associated devices are on or off with respect to each other. Both the carry and carry— signals are concurrently output. The symmetric nature of the static, dual rail, simultaneous, sum and carry circuits will improve switching performance and minimize the floating body effect that can be found in silicon on insulator (SOI) devices.

Abstract: A Schematic database defining a Schematic is checked and saved. Multiple programs affected by the Logic of the VLSI Schematic are launched along with a Checking program that extracts data related to the Logic of the VLSI Schematic design and other data that may be necessary but is not related to the Logic of the VLSI Schematic design. The Schematic design programs operate as executable program states with each program state having program data inputs and outputs and program logic inputs and outputs. Once the method is started, a designer simply corrects errors that occur and then restarts the Schematic design process If changes in the Schematic database do not affect the Logic then Logic related programs states are stopped and programs for correcting non Logic related changes are run. Program output data may be conditional with errors or unconditional without errors depending on operational modes.

Abstract: A method for automatically running a plurality of interactive programs that are necessary to complete a VLSI design and verification is disclosed. Layout data is completed and saved. Multiple programs of the VLSI logic are launched using this data. The submission of design programs (jobs) operate as programs “states” with each program state having data inputs, data outputs possibly receiving logic inputs and generating logic outputs. The data inputs and data outputs may be conditional in that they were generated from other program states that may not have executed error free. Logic routines generate the logic signals which are logic combinations of the generated logic outputs and these logic signals may be used to launch other program states. Once the method is started, a designer simply corrects errors that occur and then re-starts the design process.

Abstract: A voltage converter circuit (10) includes a primary P-type FET (20) having its source-drain conduction path connected between an input (22) and a first output node (23). An N-type FET (21) is connected in parallel with the primary P-type device (20) between the input (22) and first output node (23). The gate electrode of the primary P-type device (20) is connected to the first output node (23) while the gate electrode of the N-type device (21) is connected to a second voltage supply at the voltage level of a desired second voltage signal. A first digital signal at a first voltage level is applied to the input (22). The voltage produced at the first output node (23) equals the desired second voltage level and comprises the input signal voltage reduced by the threshold voltage of the primary P-type device (20). One or more additional P-type devices (40) may be connected in series with the primary P-type device (20) to reduce the output voltage level further.

Abstract: The present invention provides a driver/receiver pair connected as a repeater circuit which simultaneously transmits and receives information on multiple connected transmission lines. Transceiver circuits are provided which are mirror images of one another to perform the repeater function of the present invention. Each transceiver in the repeater circuit includes a non-inverting buffer stage which produces a signal swing less than the typical Vdd to ground which is typical for common CMOS inverters. The limited swing provides a variable reference input to a differential receiver element. This receiver looks at the incoming signal, and the signal being transmitted from the repeater to determine if the incoming signal is logical "1" or logical "0". This is done on each side of the repeater since the actual voltage level on the wire at the repeater terminal is a composite of the signal received by the repeater and the signal being transmitted by the repeater.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.