Abstract: A fan module including a first body, a second body, a first fan assembly, a power module, and a second fan assembly is provided. The second body is slidably disposed at the first body to form a circulation space together. The first fan assembly is rotatably disposed at the first body and has sliding grooves. The power module is disposed in the first body and connected to the first fan assembly. The second fan assembly is rotatably disposed at the second body and has sliding portions, respectively and slidably disposed in corresponding sliding grooves. The power module is adapted to drive the first and second fan assemblies to rotate relative to the first body. A link module is adapted to drive the first and second bodies to relatively slide along an axial direction, so that the first and second fan assemblies are relatively separated or overlapped along the axial direction.

Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.

Abstract: A massive testing system of a micro integrated circuit includes: a first test area including a plurality of test pads and a plurality of reading pads, and disposed on scribe lines; a plurality of test controllers disposed on the scribe lines one by one; and a probe configured to contact the first test area to test a plurality of rows of integrated circuit chips; wherein each of the plurality of test controllers is configured to test a respective one of the plurality of rows of integrated circuit chips row by row; wherein the probe merely contacts the first test area once; wherein the plurality of reading pads are configured to read test results of each of the plurality of rows of integrated circuit chips row by row.

Abstract: A shoe insole and processing method for shoe insole are disclosed. The insole includes an insole body for the stepping of the sole of one human foot. The insole body includes an upper insole layer having a top surface and an opposing bottom surface, a lower insole layer and a bulge. The upper insole layer is cold pressed to form bulges on the upper insole layer corresponding to different areas of the structure of the human foot. Then, the lower insole layer is bonded to the bottom surface of the upper insole layer, and then, perform cold pressing forming. Each bulge has a first convex surface and a first concave surface. The top surface of the upper insole layer integrally raised to form a first convex surface. The bottom surface of the upper insole layer integrally dented corresponding to the first convex surface to form a first concave surface.

Abstract: A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate structure wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate structure. The semiconductor device structure includes a source/drain structure over the fin. The source/drain structure is over a side of the gate structure and connected to the first nanostructure, the source/drain structure has an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, the upper portion has a first diamond-like shape, and the lower portion is wider than the neck portion.

Abstract: A semiconductor device includes a first fin and a second fin in a first direction and aligned in the first direction over a substrate, an isolation insulating layer disposed around lower portions of the first and second fins, a first gate electrode extending in a second direction crossing the first direction and a spacer dummy gate layer, and a source/drain epitaxial layer in a source/drain space in the first fin. The source/drain epitaxial layer is adjacent to the first gate electrode and the spacer dummy gate layer with gate sidewall spacers disposed therebetween, and the spacer dummy gate layer includes one selected from the group consisting of silicon nitride, silicon oxynitride, silicon carbon nitride, and silicon carbon oxynitride.

Abstract: A memory device is provided. The memory device includes a bottom electrode, a first data storage layer, a second data storage layer, an interfacial conductive layer and a top electrode. The first data storage layer is disposed on the bottom electrode and in contact with the bottom electrode. The second data storage layer is disposed over the first data storage layer. The interfacial conductive layer is disposed between the first data storage layer and the second data storage layer. The top electrode is disposed over the second data storage layer.

Abstract: An immersive multimedia system, an immersive interactive method and a movable interactive unit are provided in the disclosure. The immersive multimedia system includes multiple movable interactive units, an imaging apparatus, and a computer device. The multiple movable interactive units are disposed on at least one of the wall and the ground. The imaging apparatus is adapted to display an image screen on at least one of the wall and the ground. The computer device is connected to the multiple movable interactive units and the imaging apparatus. The computer device is adapted to control the multiple movable interactive units and the imaging apparatus. The multiple movable interactive units each include a touch sensing unit, and the image screen provided by the imaging apparatus changes in response to the touch sensing unit of at least one of the multiple movable interactive units sensing being touched.

Abstract: An embodiment includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first epitaxial source/drain region in the first fin and adjacent the first gate spacer, an outer surface of the epitaxial first source/drain region having more than eight facets in a first plane, the first plane being orthogonal to a top surface of the substrate.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy, gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

Abstract: An electronic apparatus including an apparatus body and a functional assembly is provided. The apparatus body has a concave. The functional assembly includes a main body and an axle. The axle is slidably disposed in the main body, and a part of the axle is adapted to protrude out of the main body to be combined with the concave. When the part of the axle is combined with the concave, the main body is adapted to rotate relative to the apparatus body by treating the axle as a rotation axis.

Abstract: A memory cell includes pair of metal layers, insulating layer, memory layer, selector layer, and word line. The pair of metal layers extends in a first direction. A first metal layer of the pair is disposed in contact with a second metal layer of the pair. The first metal layer includes a first material. The second metal layer includes a second material. The second metal layer laterally protrudes with respect to the first metal layer along a second direction perpendicular to the first direction. The insulating layer extends in the first direction and is disposed on top of the pair. The memory layer conformally covers sides of the pair. The selector layer is disposed on the memory layer. The word line extends along the second direction on the selector layer over the pair.

Abstract: A massive testing system of a micro integrated circuit includes: a first test area including a plurality of test pads and a plurality of reading pads, and disposed on scribe lines; a plurality of test controllers disposed on the scribe lines one by one; and a probe configured to contact the first test area to test a plurality of rows of integrated circuit chips; wherein each of the plurality of test controllers is configured to test a respective one of the plurality of rows of integrated circuit chips row by row; wherein the probe merely contacts the first test area once; wherein the plurality of reading pads are configured to read test results of each of the plurality of rows of integrated circuit chips row by row.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a substrate, a first nanostructure, and a second nanostructure. The method includes forming an isolation layer over the base. The method includes forming a gate dielectric layer over the first nanostructure, the second nanostructure, the fin, and the isolation layer. The method includes forming a gate electrode layer over the first part. The method includes forming a spacer layer. The method includes removing the second part of the gate dielectric layer and the first upper portion of the isolation layer to form a space between the fin and the spacer layer. The method includes forming a source/drain structure in the space and over the first nanostructure and the second nanostructure.

Abstract: A method for facilitating optimization of a cluster computing network for sequencing data analysis using adaptive data parallelization is provided. The method comprises the following steps. (a) A data parallelization configuration is determined, based on sequencing data and a pipeline selection, wherein the data parallelization configuration includes partition indication data indicating at least one biological information unit based on which of the sequencing data is to be partitioned.

Abstract: In a method of manufacturing a semiconductor device, a fin structure having a lower fin structure and an upper fin structure disposed over the lower fin structure is formed. The upper fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The first semiconductor layers are partially etched to reduce widths of the first semiconductor layers. An oxide layer is formed over the upper fin structure. A sacrificial gate structure is formed over the upper fin structure with the oxide layer. A source/drain epitaxial layer is formed over a source/drain region of the fin structure. The sacrificial gate structure is removed to form a gate space. The oxide layer is removed to expose the second semiconductor layers in the gate space. A gate structure is formed around the second semiconductor layers in the gate space.

Abstract: In an embodiment, a device includes a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes and a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer having a first dopant concentration of boron. The device also includes and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a second dopant concentration of boron, the second dopant concentration being greater than the first dopant concentration.

Abstract: The present invention provides a probe card comprising a probe base, at least one impedance-matching probes, and a plurality of first probes. The probe base has a probing side and a tester side opposite to the probing side. Each impedance-matching probe has a probing part and a signal transmitting part electrically coupled to the probing part, wherein one end of the signal transmitting part is arranged at tester side, and the signal transmitting part has a central probing axis. Each first probe has a probing tip and a cantilever part coupled to the probing tip, wherein the cantilever part is coupled to the probe base and has a first central axis such that an included angle is formed between the central probing axis and the first central axis.

Abstract: An electronic apparatus including an apparatus body and a functional assembly is provided. The apparatus body has a concave. The functional assembly includes a main body and an axle. The axle is slidably disposed in the main body, and a part of the axle is adapted to protrude out of the main body to be combined with the concave. When the part of the axle is combined with the concave, the main body is adapted to rotate relative to the apparatus body by treating the axle as a rotation axis.