Patents by Inventor Tai-Hung Lin
Tai-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11947879Abstract: An interactive information system includes: a first frame, a first interactive module arranged in the first frame, a second frame, a control module arranged in the second frame and configured to generate a graphic user interface (GUI) and to perform a function of the interactive information system based on the first user input; and a first internal cable connecting the first interactive module bridge board and the control module and configured to transmit the plurality of inter-frame signals between the first frame and the second frame. The first interactive module includes: a first display module for display of the GUI; a first touch input module configured to receive a first user input to the GUI; and a first interactive module bridge board configured to transmit a plurality of inter-frame signals comprising electrical signals of the first display module and the first touch input module.Type: GrantFiled: May 24, 2022Date of Patent: April 2, 2024Assignee: Flytech Technology Co., Ltd.Inventors: Tai-Seng Lam, Po-Hung Lin, Hsuan-Chuan Wang, Yong-Shun Kuan
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Patent number: 11581261Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.Type: GrantFiled: February 26, 2021Date of Patent: February 14, 2023Assignee: Novatek Microelectronics Corp.Inventors: Chun-Yu Liao, Teng-Jui Yu, Jr-Ching Lin, Wen-Ching Huang, Tai-Hung Lin
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Patent number: 11569162Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.Type: GrantFiled: August 10, 2020Date of Patent: January 31, 2023Assignee: Novatek Microelectronics Corp.Inventors: Chiao-Ling Huang, Tai-Hung Lin
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Patent number: 11515239Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.Type: GrantFiled: February 8, 2021Date of Patent: November 29, 2022Assignee: Novatek Microelectronics Corp.Inventors: Hong-Dyi Chang, Tai-Hung Lin, Jhih-Siou Cheng
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Publication number: 20220020673Abstract: A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.Type: ApplicationFiled: February 8, 2021Publication date: January 20, 2022Applicant: Novatek Microelectronics Corp.Inventors: Hong-Dyi Chang, Tai-Hung Lin, Jhih-Siou Cheng
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Publication number: 20210183781Abstract: A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.Type: ApplicationFiled: February 26, 2021Publication date: June 17, 2021Applicant: Novatek Microelectronics Corp.Inventors: Chun-Yu Liao, Teng-Jui Yu, Jr-Ching Lin, Wen-Ching Huang, Tai-Hung Lin
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Publication number: 20210098345Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.Type: ApplicationFiled: August 10, 2020Publication date: April 1, 2021Inventors: Chiao-Ling Huang, Tai-Hung Lin
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Patent number: 10777498Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.Type: GrantFiled: November 24, 2017Date of Patent: September 15, 2020Assignee: Novatek Microelectronics Corp.Inventors: Chiao-Ling Huang, Tai-Hung Lin
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Patent number: 10770368Abstract: A chip on film package includes a base film, a chip and a heat-dissipation structure. The base film includes a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and has a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis. The heat-dissipation structure includes a covering portion. The covering portion at least partially covers the chip, exposes a side surface of the chip, and has a first length along the first axis and a second length along the second axis being longer than the chip width of the chip. The side surface connects a top surface and a bottom surface of the chip. A heat-dissipation structure is also provided.Type: GrantFiled: August 6, 2018Date of Patent: September 8, 2020Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Tai-Hung Lin
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Publication number: 20190067168Abstract: A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.Type: ApplicationFiled: November 24, 2017Publication date: February 28, 2019Applicant: Novatek Microelectronics Corp.Inventors: Chiao-Ling Huang, Tai-Hung Lin
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Publication number: 20190020015Abstract: A lithium manganese iron phosphate-based particulate for a cathode of a lithium battery. The lithium manganese iron phosphate-based particulate includes a core portion and a shell portion. The core portion includes a plurality of first lithium manganese iron phosphate-based nanoparticles which are bound together and which have a first mean particle size. The shell portion encloses the core portion and includes a plurality of second lithium manganese iron phosphate-based nanoparticles which are bound together and which have a second mean particle size larger than the first mean particle size of the first lithium manganese iron phosphate-based nanoparticles of the core portion.Type: ApplicationFiled: August 24, 2017Publication date: January 17, 2019Inventors: Hsin-Ta Huang, Tai-Hung LIN, Yi-Hsuan WANG, Chih-Tsung Hsu
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Publication number: 20180342437Abstract: A chip on film package includes a base film, a chip and a heat-dissipation structure. The base film includes a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and has a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis. The heat-dissipation structure includes a covering portion. The covering portion at least partially covers the chip, exposes a side surface of the chip, and has a first length along the first axis and a second length along the second axis being longer than the chip width of the chip. The side surface connects a top surface and a bottom surface of the chip. A heat-dissipation structure is also provided.Type: ApplicationFiled: August 6, 2018Publication date: November 29, 2018Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Tai-Hung Lin
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Publication number: 20180331049Abstract: A chip on film package includes a base film, a patterned circuit layer, a solder resist layer, a chip and a first conductive film. The base film includes a first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The solder resist layer partially covers the patterned circuit layer. The chip is disposed in the mounting region and electrically connected to the patterned circuit layer. The first conductive film covers at least a part of the first solder resist layer and an opening exposing at least a part of the patterned circuit layer, wherein the first conductive film is configured to shield electromagnetic interference (EMI) emanating by the chip and is electrically connected to the patterned circuit layer.Type: ApplicationFiled: September 15, 2017Publication date: November 15, 2018Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Tai-Hung Lin
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Patent number: 10043737Abstract: A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.Type: GrantFiled: October 28, 2016Date of Patent: August 7, 2018Assignee: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Tai-Hung Lin
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Patent number: 9881892Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.Type: GrantFiled: January 23, 2017Date of Patent: January 30, 2018Assignee: Novatek Microelectronics Corp.Inventors: Jung-Fu Hsu, Tai-Hung Lin, Chang-Tien Tsai
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Publication number: 20170192453Abstract: A wearable device with a chip on film package structure is provided. The wearable device with the chip on film package structure includes a display device and a chip device. The display device includes a display area and a non-display area. The non-display area includes a bonding area. The chip device is bonded to the display device via the chip on film package structure. The chip device is configured to drive the display device to display images. The chip on film package structure includes a film having a first end and a second end. The chip device is located on the film, and the first end of the film is bonded to the bonding area of the display device.Type: ApplicationFiled: September 7, 2016Publication date: July 6, 2017Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Shu-Huan Hsieh, Tai-Hung Lin, Feng-Ting Pai
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Publication number: 20170162487Abstract: A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.Type: ApplicationFiled: October 28, 2016Publication date: June 8, 2017Applicant: Novatek Microelectronics Corp.Inventors: Wen-Ching Huang, Tai-Hung Lin
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Publication number: 20170133343Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.Type: ApplicationFiled: January 23, 2017Publication date: May 11, 2017Applicant: Novatek Microelectronics Corp.Inventors: Jung-Fu Hsu, Tai-Hung Lin, Chang-Tien Tsai
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Patent number: 9627337Abstract: An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.Type: GrantFiled: June 16, 2015Date of Patent: April 18, 2017Assignee: Novatek Microelectronics Corp.Inventors: Jung-Fu Hsu, Tai-Hung Lin, Chang-Tien Tsai