Patents by Inventor Tai-In Chang
Tai-In Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240176353Abstract: The present invention provides a method of alerting to stationary objects for vehicle. When a vehicle moves at a first speed, an optical scanning device, an infrared image extraction device, and an image extraction device extract a first optical scanning image, a first infrared image, and a first ambient image of the ambiance on one side of the vehicle. According to the fusion algorithm and the optical flow method, the first obstacle information of the first obstacle in the first image will be given. According to the location information of the first obstacle, the vehicle computer judges and generates an alert message when the relative distance is smaller than a distance threshold value and the obstacle volume is greater than a volume threshold value.Type: ApplicationFiled: July 6, 2023Publication date: May 30, 2024Inventors: TSUNG-HAN LEE, JINN-FENG JIANG, SHIH-CHUN HSU, TSU-KUN CHANG, CHENG-TAI LEI, HUNG-YUAN WEI
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Patent number: 11985906Abstract: A magnetic tunnel junction (MTJ) memory cell and a metallic etch mask portion are formed over a substrate. At least one dielectric etch stop layer is deposited over the metallic etch mask portion, and a via-level dielectric layer is deposited over the at least one dielectric etch stop layer. A via cavity may be etched through the via-level dielectric layer, and a top surface of the at least one dielectric etch stop layer is physically exposed. The via cavity may be vertically extended by removing portions of the at least one dielectric etch stop layer and the metallic etch mask portion. A contact via structure is formed directly on a top surface of the top electrode in the via cavity to provide a low-resistance contact to the top electrode.Type: GrantFiled: March 12, 2021Date of Patent: May 14, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu, Chung-Te Lin
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Publication number: 20240138520Abstract: A shoe insole includes an insole body for the stepping of the sole of one human foot. The insole body includes an upper insole layer having a top surface and an opposing bottom surface, a lower insole layer and a bulge. The upper insole layer is cold pressed to form bulges on the upper insole layer corresponding to different areas of the structure of the human foot. Then, the lower insole layer is bonded to the bottom surface of the upper insole layer, and then, perform cold pressing forming. Each bulge has a first convex surface and a first concave surface. The top surface of the upper insole layer integrally raised to form a first convex surface. The bottom surface of the upper insole layer integrally dented corresponding to the first convex surface to form a first concave surface.Type: ApplicationFiled: January 10, 2024Publication date: May 2, 2024Inventor: Heng-Tai CHANG
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Patent number: 11966133Abstract: An electronic device is disclosed. The electronic device includes a substrate, a plurality of color filters disposed on the substrate, an optical film disposed on the plurality of color filter, and a defect disposed between the substrate and the optical film. The optical film has a first base, a protective layer on the first base, and a second base between the first base and the protective layer and having a first processed area. In a top view of the electronic device, the first processed area corresponds to the defect and at least partially overlaps at least two color filters.Type: GrantFiled: May 18, 2023Date of Patent: April 23, 2024Assignee: INNOLUX CORPORATIONInventors: Tai-Chi Pan, Chin-Lung Ting, I-Chang Liang, Chih-Chiang Chang Chien, Po-Wen Lin, Kuang-Ming Fan, Sheng-Nan Chen
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Patent number: 11968908Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.Type: GrantFiled: June 30, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
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Patent number: 11950655Abstract: A shoe insole and processing method for shoe insole are disclosed. The insole includes an insole body for the stepping of the sole of one human foot. The insole body includes an upper insole layer having a top surface and an opposing bottom surface, a lower insole layer and a bulge. The upper insole layer is cold pressed to form bulges on the upper insole layer corresponding to different areas of the structure of the human foot. Then, the lower insole layer is bonded to the bottom surface of the upper insole layer, and then, perform cold pressing forming. Each bulge has a first convex surface and a first concave surface. The top surface of the upper insole layer integrally raised to form a first convex surface. The bottom surface of the upper insole layer integrally dented corresponding to the first convex surface to form a first concave surface.Type: GrantFiled: May 20, 2021Date of Patent: April 9, 2024Assignee: DAH SHENG CHEMICAL INDUSTRY CO., LTD.Inventor: Heng-Tai Chang
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Publication number: 20240103578Abstract: A control assembly configured for an electronic device, the control assembly includes a mount seat configured to be installed on the electronic device, two first connection components movably connected to the mount seat, two second connection component movably connected to the two first connection components, respectively, two controllers configured to communicate with the electronic device, the two controllers are separated apart from each other and movably connected to the second connection components, respectively, such that the two controllers are connected to the mount seat via the two second connection components and the two first connection components.Type: ApplicationFiled: November 25, 2022Publication date: March 28, 2024Applicant: DEXIN CORP.Inventors: Ho Lung LU, Chiu Tai CHANG, Min-Chien CHANG
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Patent number: 11940388Abstract: Example methods are provided to improve placement of an adaptor (210,220) to a mobile computing device (100) to measure a test strip (221) coupled to the adaptor (220) with a camera (104) and a screen (108) on a face of the mobile computing device (100). The method may include displaying a light area on a first portion of the screen (108). The first portion may be adjacent to the camera (104). The light area and the camera (104) may be aligned with a key area of the test strip (221) so that the camera (104) is configured to capture an image of the key area. The method may further include providing first guiding information for a user to place the adaptor (210,220) to the mobile computing device (100) according to a position of the light area on the screen (108).Type: GrantFiled: March 16, 2018Date of Patent: March 26, 2024Assignee: IXENSOR CO., LTD.Inventors: Yenyu Chen, An Cheng Chang, Tai I Chen, Su Tung Yang, Chih Jung Hsu, Chun Cheng Lin, Min Han Wang, Shih Hao Chiu
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Publication number: 20240079121Abstract: A TRS workflow is registered in a cloud-native biomedical informatics platform, and the TRS workflow includes at least one TRS_FQN. A workflow automation execution method applied in the cloud-native biomedical informatics platform includes providing a run sheet used to configure a sequencer to generate a first sequencing data. The run sheet includes a sample-specific metadata associating the first sequencing data, at least one TRS_FQN and a run identifier. The method further includes importing a first DRS object indicating the first sequencing data in response to the run sheet. A first WES_FQN is generated based on the run identifier and the at least one TRS_FQN and attached to the first DRS object. The method further includes performing a WES run running the TRS workflow on the first DRS object in response to the run sheet. The first DRS object is resolved based on the first WES_FQN.Type: ApplicationFiled: August 28, 2023Publication date: March 7, 2024Inventors: Ming-Tai CHANG, Yun Lung LI
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Publication number: 20240076417Abstract: The present disclosure provides a method for manufacturing an auto-crosslinked hyaluronic acid gel, comprising conducting auto-crosslinking reaction of a colloid containing hyaluronic acid continuously at low temperature in an acidic environment, and treating the reaction product with steam at high temperature to obtain the auto-crosslinked hyaluronic acid gel with high viscosity.Type: ApplicationFiled: September 5, 2023Publication date: March 7, 2024Applicant: SCIVISION BIOTECH INC.Inventors: TAI-SHIEN HAN, TSUNG-WEI PAN, TOR-CHERN CHEN, CHUN-CHANG CHEN, PO-HSUAN LIN, LI-SU CHEN
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Patent number: 11921947Abstract: A touch function setting method is provided. The method comprising: receiving a sequence parameter which includes multiple clicks, each of the clicks is corresponding to one of areas of a touch panel or screen; receiving a function parameter corresponding to the sequence parameter, the function parameter is corresponding to activate a function; and storing a group of touch function parameters, which includes the sequence parameter and the function parameter.Type: GrantFiled: February 18, 2022Date of Patent: March 5, 2024Assignee: EGALAX_EMPIA TECHNOLOGY INC.Inventors: Chin-Fu Chang, Shang-Tai Yeh, Chia-Ling Sun, Jia-Ming Chen
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Publication number: 20240074027Abstract: A capacitor capable of releasing reactive oxygen species and reactive nitrogen species after powering of claim 1 is composed of the dielectric material. A plurality of through holes are designed on the capacitor, the through holes being used as air gaps to supply plasma gas and blow a fan to increase the gas flow, and the voltage being connected to the two corresponding electrode edges of the capacitor so that the capacitor generating a heating temperature (lower than 200 degrees Celsius). Thereby, after the capacitor is perforated to form honeycomb shape and powered, the air surrounding the capacitor flowing through the capacitor is ionized to the oxygen ion and nitrogen ion via heating and charge-discharge, generates plasma at room temperature and atmospheric pressure and releases the reactive oxygen ions and reactive nitrogen ions healing and helpful for body healing.Type: ApplicationFiled: August 23, 2022Publication date: February 29, 2024Inventors: Chung-Tai Chang, Chia-Hao Chang, Ting-Yi Chang
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Publication number: 20240012816Abstract: A method for automating multimodal computational workflows enables an analysis process of an instruction set to be performed automatically in a cloud environment. Localizing step includes configuring a loader to load a dataset into dataframes of a memory or copy the dataset to a local host file system from a data source; configuring a transformer to transform the dataframes of the memory into a transformed dataset; configuring a formatter to format the transformed dataset to a formatted dataset; and configuring an executor to preprocess the formatted dataset as a managed table for a first command or save the formatted dataset to the local host file system for a second command. Delocalizing step includes configuring a collector to postprocess the command outputs outputted from the memory or retrieve the command outputs from the local host file system; and configuring a writer to save the command outputs to a storage.Type: ApplicationFiled: July 6, 2023Publication date: January 11, 2024Inventors: Ming-Tai CHANG, Wen-Chien WENG, Yu-Ting LIN
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Semiconductor memory devices with electrically isolated stacked bit lines and methods of manufacture
Patent number: 11849655Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.Type: GrantFiled: July 23, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang -
Patent number: 11848365Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure includes a gate structure wrapping around a top portion of the fin. The semiconductor device structure includes a first nanostructure over the fin and passing through the gate structure. The semiconductor device structure includes a source/drain structure over the fin. The source/drain structure is over a side of the gate structure and connected to the first nanostructure, the source/drain structure has an upper portion, a lower portion, and a neck portion between the upper portion and the lower portion, the upper portion has a first diamond-like shape, and the lower portion is wider than the neck portion.Type: GrantFiled: June 6, 2022Date of Patent: December 19, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tung-Ying Lee, Kai-Tai Chang
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Publication number: 20230387071Abstract: A method includes determining a first offset between a first alignment mark on a first side of a first wafer and a second alignment mark on a second side of the first wafer; aligning the first alignment mark of the first wafer to a third alignment mark on a first side of a second wafer, which includes detecting a location of the second alignment mark of the first wafer; determining a location of the first alignment mark of the first wafer based on the first offset and the location of the second alignment mark of the first wafer; and, based on the determined location of the first alignment mark, repositioning the first wafer to align the first alignment mark to the third alignment mark; and bonding the first side of the first wafer to the first side of the second wafer to form a bonded structure.Type: ApplicationFiled: July 26, 2023Publication date: November 30, 2023Inventors: Kai-Tai Chang, Tung Ying Lee
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SEMICONDUCTOR MEMORY DEVICES WITH ELECTRICALLY ISOLATED STACKED BIT LINES AND METHODS OF MANUFACTURE
Publication number: 20230380310Abstract: A semiconductor device includes a memory structure over a substrate, wherein the memory structure includes a first word line; a first bit line over the first word line; a second bit line over the first bit line; a memory material over sidewalls of the first bit line and the second bit line; a first control word line along a first side of the memory material, wherein the first control word line is electrically connected to the first word line; a second control word line along a second side of the memory material that is opposite the first side; and a second word line over the second bit line, the first control word line, and the second control word line, wherein the second word line is electrically connected to the second control word line.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Tung Ying Lee, Shao-Ming Yu, Kai-Tai Chang -
Publication number: 20230371400Abstract: A memory device and a method of manufacturing the same are provided. The memory device includes a semiconductor substrate, an interconnect structure and a memory cell. The interconnect structure is disposed over the semiconductor substrate, and the memory cell is disposed over the interconnect structure and electrically coupled with the semiconductor substrate and the interconnect structure. The memory cell includes a spin Hall electrode layer, an MTJ pillar, a hard mask, and a spacer. The MTJ pillar is disposed on the spin Hall electrode layer, the hard mask is disposed on the MTJ pillar, and the spacer is disposed on sidewalls of the MTJ pillar and the hard mask. Suitably, the spin Hall electrode layer at least comprises an inner portion and an outer portion surrounding the inner portion, and a top surface of the outer portion is lower than a top surface of the inner portion.Type: ApplicationFiled: May 16, 2022Publication date: November 16, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Kai-Tai Chang, Chien-Min Lee, Tung-Ying Lee, Shy-Jay Lin