Abstract: A driving substrate includes a substrate, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the substrate. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

Abstract: A driving substrate includes a base material, a plurality of active devices, a thermal-conducting pattern layer and a buffer layer. The active devices are separately arranged on the base material. Each active device includes a gate, a channel layer, a gate insulation layer, a source and a drain. The source and the drain expose a portion of the channel layer to define a channel region. The thermal-conducting pattern layer is disposed on the substrate and includes at least one thermal-conducting body and at least one thermal-conducting pattern connected to the thermal-conducting body. The thermal-conducting pattern corresponds to a location of at least one of the channel region, the channel layer, the gate, the source and the drain and each active device. The buffer layer is disposed on the substrate and covers the thermal-conducting pattern layer, and is located between the thermal-conducting pattern and each active device.

Abstract: A display panel and a method for inspecting thereof are provided. The display panel includes a first signal circuit, a second signal circuit and a plurality of first resistor. The first signal circuit includes a plurality of first signal lines which disposes in parallel along a first direction and electrically connects to one another. The second signal circuit includes a plurality of second signal lines disposing in parallel along the first direction, and the second signal lines and the first signal lines are alternately disposed in parallel. Each of second signal lines is connected to at least a first resistor. The interval between the first signal line and the second signal line is smaller than 60 ?m and the difference between the resistances of the first signal line and the second signal line is ranged form 300 ohm to 30000 ohm.