Abstract: A coil component is provided. The coil component includes a body having fifth and sixth surfaces opposing each other, first and second surfaces respectively connecting the fifth and sixth surfaces of the body and opposing each other, and third and fourth surfaces respectively connecting the first and second surfaces of the body and opposing each other in one direction, a recess disposed in an edge between one of the first and second surfaces of the body and the sixth surface of the body, a coil portion disposed inside the body and exposed through the recess, and an external electrode including a connection portion disposed in the recess and connected to the coil portion, and a pad portion disposed on one surface of the body. A length of the pad portion in the one direction is greater than a length of the connection portion in the one direction.

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

Abstract: Provided is a semiconductor device, including gate structures on a substrate, the gate structures extending parallel to a first direction and being spaced apart from each other by a separation trench interposed therebetween, each of the gate structures including insulating patterns stacked on the substrate and a gate electrode interposed therebetween; vertical pillars connected to the substrate through the gate structures; an insulating spacer in the separation trench covering a sidewall of each of the gate structures; and a diffusion barrier structure between the gate electrode and the insulating spacer.

Abstract: Provided are a semiconductor memory device and a fabricating method thereof. The device includes a stack including vertical channel structures that penetrate insulating patterns and gate electrodes that are alternately and repeatedly stacked on each other. Each of the gate electrodes includes first and second gate conductive layers. In a first region between an outer side of the stack and the vertical channel structures, the first gate conductive layer is adjacent to the vertical channel structures and includes a truncated end portion, the second gate conductive layer has a portion adjacent to the vertical channel structures and covered by a corresponding one of the first gate conductive layer and an opposite portion that is not covered with the first gate conductive layer. In a second region between the vertical channel structures, the first gate conductive layer may be extended to continuously cover surfaces of the second gate conductive layer.

Abstract: A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer.

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method may include forming an electrode structure including insulating layers and electrode layers alternatingly stacked on a substrate, forming a channel hole to penetrate the electrode structure, forming a data storage layer on a sidewall of the channel hole, and forming a semiconductor pattern on a sidewall of the data storage layer to be electrically connected to the substrate. The electrode layers may be metal-silicide layers, and the insulating layers and the electrode layers may be formed in an in-situ manner using the same deposition system.

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract: A semiconductor device may include a contact mold layer on a substrate, the contact mold layer defining first and second contact portions on the substrate, a wire mold layer on the contact mold layer, and first and second wires penetrating the wire mold layer and extending in a first direction, the first and second wires contacting the respective first and second contact portions and the contact mold layer. The first and second wires may be arranged in an alternating manner, and the first and second contact portions may be arranged to have a zigzag configuration. Each of the first and second contact portions may include a conductive pattern and a barrier pattern, and the barrier pattern may have a top surface lower than a top surface of the contact mold layer.

Abstract: A semiconductor device includes a substrate, a first poly-silicon pattern on the substrate, a metal pattern on the first poly-silicon pattern, and an interface layer between the first poly-silicon pattern and the metal pattern. The interface layer may include at least one selected from the group of a metal-silicon oxynitride layer, a metal-silicon oxide layer, and a metal-silicon nitride layer.

Abstract: A nonvolatile memory device includes a memory gate pattern on a substrate, and a non-memory gate pattern on the substrate, the non-memory gate pattern being spaced apart from the memory gate pattern, wherein the non-memory gate pattern includes an ohmic layer, and the memory gate pattern is provided without an ohmic layer.

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract: A phase-change memory device, including a lower electrode, a phase-change material pattern electrically connected to the lower electrode, and an upper electrode electrically connected to the phase-change material pattern. The lower electrode may include a first structure including a metal semiconductor compound, a second structure on the first structure, the second structure including a metal nitride material, and including a lower part having a greater width than an upper part, and a third structure including a metal nitride material containing an element X, the third structure being on the second structure, the element X including at least one selected from the group of silicon, boron, aluminum, oxygen, and carbon.

Abstract: Methods of forming a semiconductor device include forming an insulation layer on a semiconductor structure, forming an opening in the insulation layer, the opening having a sidewall defined by one side of the insulation layer, forming a first metal layer in the opening, at least partially exposing the sidewall of the opening by performing a wet-etching process on the first metal layer, and selectively forming a second metal layer on the etched first metal layer. An average grain size of the first metal layer is smaller than an average grain size of the second metal layer. Related semiconductor devices are also disclosed.

Abstract: In the method of fabricating the variable-resistance memory device, a substrate including a conductive region is provided, and a preliminary lower electrode is formed on the conductive region. A lower electrode is formed by oxidizing an upper portion of the preliminary lower electrode. A phase-change material layer is formed on the lower electrode.