Patents by Inventor Tai-Yi CHEN
Tai-Yi CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Patent number: 11968908Abstract: In an embodiment, a method includes: forming a first inter-metal dielectric (IMD) layer over a semiconductor substrate; forming a bottom electrode layer over the first IMD layer; forming a magnetic tunnel junction (MTJ) film stack over the bottom electrode layer; forming a first top electrode layer over the MTJ film stack; forming a protective mask covering a first region of the first top electrode layer, a second region of the first top electrode layer being uncovered by the protective mask; forming a second top electrode layer over the protective mask and the first top electrode layer; and patterning the second top electrode layer, the first top electrode layer, the MTJ film stack, the bottom electrode layer, and the first IMD layer with an ion beam etching (IBE) process to form a MRAM cell, where the protective mask is etched during the IBE process.Type: GrantFiled: June 30, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Han-Ting Lin, Sin-Yi Yang, Yu-Shu Chen, An-Shen Chang, Qiang Fu, Chen-Jung Wang
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Publication number: 20240128420Abstract: A display panel including a circuit board, a plurality of bonding pads, a plurality of light emitting devices, and a plurality of solder patterns is provided. The bonding pads are disposed on the circuit board, and each includes a first metal layer and a second metal layer. The second metal layer is located between the first metal layer and the circuit board. The first metal layer includes an opening overlapping the second metal layer. A material of the first metal layer is different from a material of the second metal layer. The light emitting devices are electrically bonded to the bonding pads. Each of the solder patterns electrically connects one of the light emitting devices and one of the bonding pads. The solder patterns each contact the second metal layer through the opening of the first metal layer of one of the bonding pads to form a eutectic bonding.Type: ApplicationFiled: December 6, 2022Publication date: April 18, 2024Applicant: AUO CorporationInventors: Chia-Hui Pai, Tai-Tso Lin, Wen-Hsien Tseng, Wei-Chieh Chen, Kuan-Yi Lee, Chih-Chun Yang
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Patent number: 11944017Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an insulation layer. A bottom electrode via is disposed in the insulation layer. The bottom electrode via includes a conductive portion and a capping layer over the conductive portion. A barrier layer surrounds the bottom electrode via. A magnetic tunneling junction (MTJ) is disposed over the bottom electrode via.Type: GrantFiled: May 5, 2023Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yen Peng, Yu-Shu Chen, Chien Chung Huang, Sin-Yi Yang, Chen-Jung Wang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240099150Abstract: A method includes forming Magnetic Tunnel Junction (MTJ) stack layers, which includes depositing a bottom electrode layer; depositing a bottom magnetic electrode layer over the bottom electrode layer; depositing a tunnel barrier layer over the bottom magnetic electrode layer; depositing a top magnetic electrode layer over the tunnel barrier layer; and depositing a top electrode layer over the top magnetic electrode layer. The method further includes patterning the MTJ stack layers to form a MTJ; and performing a passivation process on a sidewall of the MTJ to form a protection layer. The passivation process includes reacting sidewall surface portions of the MTJ with a process gas comprising elements selected from the group consisting of oxygen, nitrogen, carbon, and combinations thereof.Type: ApplicationFiled: November 28, 2023Publication date: March 21, 2024Inventors: Tai-Yen Peng, Yu-Shu Chen, Sin-Yi Yang, Chen-Jung Wang, Chien Chung Huang, Han-Ting Lin, Jyu-Horng Shieh, Qiang Fu
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Publication number: 20240096781Abstract: A package structure including a semiconductor die, a redistribution circuit structure and an electronic device is provided. The semiconductor die is laterally encapsulated by an insulating encapsulation. The redistribution circuit structure is disposed on the semiconductor die and the insulating encapsulation. The redistribution circuit structure includes a colored dielectric layer, inter-dielectric layers and redistribution conductive layers embedded in the inter-dielectric layers. The electronic device is disposed over the colored dielectric layer and electrically connected to the redistribution circuit structure.Type: ApplicationFiled: March 20, 2023Publication date: March 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Ti Lu, Hao-Yi Tsai, Chia-Hung Liu, Yu-Hsiang Hu, Hsiu-Jen Lin, Tzuan-Horng Liu, Chih-Hao Chang, Bo-Jiun Lin, Shih-Wei Chen, Hung-Chun Cho, Pei-Rong Ni, Hsin-Wei Huang, Zheng-Gang Tsai, Tai-You Liu, Po-Chang Shih, Yu-Ting Huang
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Publication number: 20230274074Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; modifying a pillar density of the initial power delivery network repeatedly when the circuit design does not meet the predetermined specification until the circuit design meets the predetermined specification to generate a circuit layout of the integrated circuit; and performing a post-layout simulation to the circuit layout.Type: ApplicationFiled: May 5, 2023Publication date: August 31, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chieh YANG, Tai-Yi CHEN, Yun-Ru CHEN, Yung-Chow PENG
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Patent number: 11681854Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.Type: GrantFiled: March 24, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chieh Yang, Tai-Yi Chen, Yun-Ru Chen, Yung-Chow Peng
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Publication number: 20230186008Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting LU, Chih-Chiang CHANG, Chung-Peng HSIEH, Chung-Chieh YANG, Yung-Chow PENG, Yung-Shun CHEN, Tai-Yi CHEN, Nai Chen CHENG
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Patent number: 11670672Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.Type: GrantFiled: May 3, 2021Date of Patent: June 6, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Yi Chen, Chung-Chieh Yang, Yung-Chow Peng
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Patent number: 11574104Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: GrantFiled: December 28, 2020Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting Lu, Chih-Chiang Chang, Chung-Peng Hsieh, Chung-Chieh Yang, Yung-Chow Peng, Yung-Shun Chen, Tai-Yi Chen, Nai Chen Cheng
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Publication number: 20220285265Abstract: An integrated circuit structure includes a first capacitor structure, disposed in a first layer on a semiconductor substrate and comprising a plurality of capacitors; a second capacitor structure, adjacent to first capacitor structure in the first layer, wherein the second capacitor structure and the first capacitor structure are arranged as a. strip-shaped structure; a first conductive plate, disposed at one end of the strip-shaped structure in the first layer; and a second conductive plate, disposed in a second layer on the semiconductor substrate over the strip-shaped structure and extending toward the other end of the strip-shaped structure from the one end of the strip-shaped structure.Type: ApplicationFiled: May 24, 2022Publication date: September 8, 2022Inventors: TAI-YI CHEN, YUNG-CHOW PENG, CHUNG-CHIEH YANG
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Publication number: 20220215152Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; generating a circuit layout of the integrated circuit when the circuit design meets the predetermined specification; and adding at least one additional conductive pillar or at least one additional power rail in the initial power delivery network according to a relationship of a pillar density of the initial power delivery network and a maximum pillar density when the circuit design does not meet the predetermined specification.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chieh YANG, Tai-Yi CHEN, Yun-Ru CHEN, Yung-Chow PENG
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Patent number: 11362029Abstract: An integrated circuit structure includes a first conductive plate, a second conductive plate, a plurality of conductive lines, and a plurality of conductive vias. The first conductive plate is disposed in a first layer on a semiconductor substrate. The second conductive plate is disposed in a second layer on the semiconductor substrate. The plurality of conductive lines are disposed in the first layer for surrounding the first conductive plate. The plurality of conductive vias are arranged to couple the plurality of conductive lines to the second conductive plate. The second layer is different from the first layer, and the first conductive plate is physically separated from the second conductive plate, the plurality of conductive lines, and the plurality of conductive vias.Type: GrantFiled: December 8, 2020Date of Patent: June 14, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Tai-Yi Chen, Yung-Chow Peng, Chung-Chieh Yang
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Patent number: 11308255Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.Type: GrantFiled: May 28, 2020Date of Patent: April 19, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chieh Yang, Tai-Yi Chen, Yun-Ru Chen, Yung-Chow Peng
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Publication number: 20210373059Abstract: Systems and methods are described herein for charge-based capacitor measurement. The system includes a first pseudo-inverter circuit and a second pseudo-inverter circuit. The system also includes a control circuit coupled between the first inverter circuit and the second inverter circuit. The control circuit is configured to generate independent and non-overlapping control signals for the first pseudo-inverter circuit and the second pseudo-inverter circuit. A shielding metal is coupled to the first pseudo-inverter circuit, the second pseudo-inverter circuit, and the control circuit. The shielding metal is configured to dissipate parasitic capacitance of at least one of the first pseudo-inverter circuit or the second pseudo-inverter circuit. A device under test is coupled to each of the first inverter circuit and the second inverter circuit.Type: ApplicationFiled: April 15, 2021Publication date: December 2, 2021Inventors: Tai-Yi Chen, Chung-Chieh Yang, Chih-Chiang Chang, Chung-Ting Lu
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Publication number: 20210374318Abstract: A method is disclosed including: generating, based on design information for an integrated circuit, a circuit design that includes an initial power delivery network (PDN) for the integrated circuit; performing a pre-layout simulation to the circuit design that includes the initial power delivery network, to determine whether the circuit design meets a predetermined specification; and when the circuit design meets the predetermined specification, generating a power delivery network layout of the integrated circuit, and generating, after the power delivery network layout is generated, a circuit layout of the integrated circuit.Type: ApplicationFiled: May 28, 2020Publication date: December 2, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Chieh YANG, Tai-Yi CHEN, Yun-Ru CHEN, Yung-Chow PENG
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Patent number: 11123534Abstract: A needle-free connector including a guiding base, a connecting base, a valve member, and a seal member is provided. The guiding base has a conduit, and the conduit extends downward along an axial direction. The connecting base is disposed on the guiding base and has a screw portion and a passage running through the screw portion. A chamber is formed between the guiding base and the connecting base, and the conduit and the passage respectively communicate with the chamber along the axial direction. The valve member is disposed between the guiding base and the connecting base, and is movably located in the chamber. The seal member is disposed at an end of the valve member far away from the conduit, and the seal member and the valve member are adapted to be connected into a whole in a manufacturing process.Type: GrantFiled: April 29, 2019Date of Patent: September 21, 2021Inventor: Tai-Yi Chen
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Publication number: 20210257444Abstract: Capacitor structures with low capacitances are disclosed. In one example, a capacitor structure is disclosed. The capacitor structure includes a first electrode and a second electrode. The first electrode comprises a first metal finger. The second electrode comprises a second metal finger and a third metal finger that are parallel to each other and to the first metal finger. The first metal finger is formed between the second metal finger and the third metal finger. The capacitor structure further includes: a fourth metal finger formed as a dummy metal finger between the first metal finger and the second metal finger, and a fifth metal finger formed as a dummy metal finger between the first metal finger and the third metal finger. The fourth metal finger and the fifth metal finger are parallel to the first metal finger.Type: ApplicationFiled: May 3, 2021Publication date: August 19, 2021Inventors: Tai-Yi CHEN, Chung-Chieh YANG, Yung-Chow PENG
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Publication number: 20210224459Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.Type: ApplicationFiled: December 28, 2020Publication date: July 22, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Ting LU, Chih-Chiang CHANG, Chung-Peng HSIEH, Chung-Chieh YANG, Yung-Chow PENG, Yung-Shun CHEN, Tai-Yi CHEN, Nai Chen CHENG