Patents by Inventor Tai-Yuan Wu
Tai-Yuan Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9373789Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.Type: GrantFiled: October 22, 2014Date of Patent: June 21, 2016Assignee: Industrial Technology Research InstituteInventors: Heng-Yuan Lee, Pang-Shiu Chen, Tai-Yuan Wu, Ching-Chiun Wang
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Patent number: 9257641Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.Type: GrantFiled: September 17, 2014Date of Patent: February 9, 2016Assignee: Industrial Technology Research InstituteInventors: Frederick T. Chen, Tai-Yuan Wu, Yu-Sheng Chen, Wei-Su Chen, Pei-Yi Gu, Yu-De Lin
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Publication number: 20150280122Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a structure comprising a substrate, a bottom electrode disposed on the substrate, a metal oxide layer disposed on the bottom electrode, and an oxygen atom gettering layer disposed on the metal oxide layer; and subjecting the structure to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.Type: ApplicationFiled: June 9, 2015Publication date: October 1, 2015Inventors: Heng-Yuan LEE, Pang-Shiu CHEN, Tai-Yuan WU, Ching-Chiun WANG
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Patent number: 9142776Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.Type: GrantFiled: December 20, 2012Date of Patent: September 22, 2015Assignee: Industrial Technology Research InstituteInventors: Heng-Yuan Lee, Pang-Shiu Chen, Tai-Yuan Wu, Ching-Chiun Wang
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Publication number: 20150129827Abstract: Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.Type: ApplicationFiled: September 17, 2014Publication date: May 14, 2015Inventors: Frederick T. Chen, Tai-Yuan Wu, Yu-Sheng Chen, Wei-Su Chen, Pei-Yi Gu, Yu-De Lin
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Publication number: 20150044851Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes forming a bottom electrode on a substrate; forming a metal oxide layer on the bottom electrode; forming an oxygen atom gettering layer on the metal oxide layer; forming a first top electrode sub-layer on the oxygen atom gettering layer; forming a second top electrode sub-layer on the first top electrode sub-layer, wherein the first top electrode sub-layer and the second top electrode sub-layer comprise a top electrode; and subjecting the metal oxide layer and the oxygen atom gettering layer to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, resulting in a plurality of oxygen vacancies within the metal oxide layer.Type: ApplicationFiled: October 22, 2014Publication date: February 12, 2015Inventors: HENG-YUAN LEE, PANG-SHIU CHEN, TAI-YUAN WU, CHING-CHIUN WANG
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Publication number: 20140077149Abstract: A resistance memory cell including a variable resistance layer is provided. The variable resistance layer includes at least one dominant resistance layer and at least one auxiliary resistance layer. The dominant resistance layer(s) and the auxiliary resistance layer(s) in totality form a closed ion exchange system, the exchanged ions are comparably mobile in each of the dominant resistance layer(s) and the auxiliary resistance layer(s), and the maximum resistance of the at least one dominant resistance layer is higher than that of the at least one auxiliary resistance layer.Type: ApplicationFiled: September 14, 2012Publication date: March 20, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Frederick T. Chen, Heng-Yuan Lee, Yu-Sheng Chen, Wei-Su Chen, Tai-Yuan Wu, Pang-Hsu Chen
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Publication number: 20130320289Abstract: A resistance random access memory including a first electrode layer, a second electrode layer, and a stacked structure is provided. The stacked structure includes a HfZrON layer and a ZrON layer and is located between the first electrode layer and the second electrode layer. In addition, the disclosure further provides a method of fabricating a resistance random access memory.Type: ApplicationFiled: September 13, 2012Publication date: December 5, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wei-Su Chen, Tai-Yuan Wu, Frederick T. Chen, Pang-Hsu Chen
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Patent number: 8362454Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.Type: GrantFiled: December 12, 2008Date of Patent: January 29, 2013Assignee: Industrial Technology Research InstituteInventors: Hengyuan Lee, Pang-Hsu Chen, Tai-Yuan Wu, Ching-Chiun Wang
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Patent number: 7799653Abstract: A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer tType: GrantFiled: July 25, 2008Date of Patent: September 21, 2010Assignee: Industrial Technology Research InstituteInventors: Heng-Yuan Lee, Ching-Chiun Wang, Tai-Yuan Wu
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Publication number: 20100164062Abstract: A method of manufacturing through-silicon-via (TSV) and a TSV structure are provided. The TSV structure includes a silicon substrate, an annular capacitor, a conductive through-via, a layer of low-k material, and a bump. The annular capacitor is within the silicon substrate and constituted of a first conductive layer, a capacitor dielectric layer, and a second conductive layer from the inside to the outside. The conductive through-via is disposed in the silicon substrate surrounded by the annular capacitor, and the layer of low-k material is between the annular capacitor and the conductive through-via. The bump is in touch with the conductive through-via for bonding other chip.Type: ApplicationFiled: June 9, 2009Publication date: July 1, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ching-Chiun Wang, Tai-Yuan Wu, Yu-Sheng Chen, Cha-Hsin Lin
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Publication number: 20100038791Abstract: A resistive random access memory and a method for fabricating the same are provided. The method includes providing a bottom electrode formed on a substrate. A metal oxide layer is formed on the bottom electrode. An oxygen atom gettering layer is formed on the metal oxide layer. A top electrode is formed on the oxygen atom gettering layer. The previous mentioned structure is subjected to a thermal treatment, driving the oxygen atoms of the metal oxide layer to migrate into and react with the oxygen atom gettering layer, thus leaving a plurality of oxygen vacancies of the metal oxide layer.Type: ApplicationFiled: December 12, 2008Publication date: February 18, 2010Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Hengyuan Lee, Pang-Hsu Chen, Tai-Yuan Wu, Ching-Chiun Wang
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Publication number: 20090191685Abstract: A method for forming a capacitor in a dynamic random access memory, comprising steps of: providing a semiconductor substrate having at least a transistor, whereon an interlayer dielectric layer having at least a first plug is formed so that the first plug is connected to the drain of the transistor; depositing an etching stop layer on the first plug and the interlayer dielectric layer; depositing a first insulating layer on the etching stop layer; forming at least a second plug on the first insulating layer and the etching stop layer so that the second plug is connected to the first plug; depositing a second insulating layer on the first insulating layer and the second plug; forming at least a mold cavity in the second insulating layer so that the aperture of the mold cavity is larger than the diameter of the second plug and there is a deviation between the mold cavity and the second plug; removing the first insulating layer in the mold cavity until the etching stop layer; depositing a first electrode layer tType: ApplicationFiled: July 25, 2008Publication date: July 30, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Heng-Yuan LEE, Ching-Chiun WANG, Tai-Yuan WU
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Publication number: 20090114899Abstract: A resistance memory is manufactured using semiconductor processing to comprise planar dual-tip electrodes so that the electric field in the resistance memory is concentrated to reduce the number of fuses in the dielectric material and improve the device characteristics. The resistance memory comprises: a first memory cell including a first bottom electrode and a common top electrode; and a second memory cell including a second bottom electrode and the common top electrode shared with the first memory cell; wherein the first bottom electrode, the second bottom electrode and the common top electrode are disposed on the same plane and are separated by a resistive conversion layer; wherein the common top electrode is connected to the ground through a via, while the first bottom electrode and the second bottom electrode are connected to the source of a transistor through a plug, respectively.Type: ApplicationFiled: June 19, 2008Publication date: May 7, 2009Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: HENG-YUAN LEE, CHING-CHIUN WANG, PANG-HSU CHEN, TAI-YUAN WU
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Patent number: 6623911Abstract: A method for forming a clear code mark that is independent of backend planarization by adding an extra exposing step to the normal photolithography process is described. A layer to be patterned is provided on a substrate. A photoresist layer is coated overlying the layer to be patterned. The photoresist layer is first exposed through a code mask and second exposed through a patterning mask. The photoresist layer is developed to form a photoresist mask having a code mark pattern from the code mask and a device pattern from the patterning mask. The layer to be patterned is etched away where it is not covered by the photoresist mask to form simultaneously device structures and a code mark in the fabrication of an integrated circuit device.Type: GrantFiled: September 17, 2001Date of Patent: September 23, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Chang Jong, Tai-Yuan Wu
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Patent number: 6531374Abstract: Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.Type: GrantFiled: August 10, 2001Date of Patent: March 11, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Kun-I Lee, Tai-Yuan Wu, Ren-Jyh Leu, Hung-Chih Chen
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Publication number: 20030032256Abstract: Correction of overlay shift of an epitaxial silicon layer deposited on a semiconductor wafer, and of post-epitaxial silicon layers subsequently deposited, is disclosed. When an epitaxial silicon layer of a given thickness is deposited, the zero mark coordinates for the deposition are shifted relative to alignment marks on the wafer by a distance based on the thickness of the layer. The distance is preferably proportional to the thickness of the epi layer. This prevents overlay shift of the epi layer. For post-epitaxial silicon layers subsequently deposited, preferably except for the first post-epi layer, a clear out process is initially performed to maintain the alignment marks on the semiconductor wafer. In this way, overlay shift, or misalignment, of the post-epi layers is also prevented.Type: ApplicationFiled: August 10, 2001Publication date: February 13, 2003Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kun-I Lee, Tai-Yuan Wu, Ren-Jyh Leu, Hung-Chih Chen