Patents by Inventor Taichi Nakamura

Taichi Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160003551
    Abstract: The heat exchanger is provided with a body, multiple heat transfer tubes (20) which are arranged inside of the body, and multiple support plates (30) which are arranged at intervals along the longitudinal direction of the heat transfer tubes (20) and in which multiple tube insertion through-holes (40) for inserting the multiple heat transfer tubes (20) are formed. Between two support plates (30) adjacent in the longitudinal direction among the plurality of support plates (30), the shapes of the tube insertion through-holes (40) for one heat transfer tube (20) are different.
    Type: Application
    Filed: February 17, 2014
    Publication date: January 7, 2016
    Inventors: Issaku FUJITA, Taichi NAKAMURA, Satoshi HIRAOKA
  • Patent number: 9199340
    Abstract: Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3?[Ag]?4.0, Bi satisfying 0?[Bi]?1.0, and Cu satisfying 0?[Cu]?1.2, where contents (mass %) of Ag, Bi, Cu and In in the solder material are denoted by [Ag], [Bi], [Cu], and [In], respectively. The solder material includes In in a range of 6.0?[In]?6.8 when [Cu] falls within a range of 0<[Cu]<0.5, In in a range of 5.2+(6?(1.55×[Cu]+4.428))?[In]?6.8 when [Cu] falls within a range of 0.5?[Cu]?1.0, In in a range of 5.2?[In]?6.8 when [Cu] falls within a range of 1.0<[Cu]?1.2. A balance includes only not less than 87 mass % of Sn.
    Type: Grant
    Filed: November 23, 2014
    Date of Patent: December 1, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Akio Furusawa, Kiyohiro Hine, Masato Mori, Taichi Nakamura
  • Publication number: 20150144388
    Abstract: Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3?[Ag]?4.0, Bi satisfying 0?[Bi]?1.0, and Cu satisfying 0?[Cu]?1.2, where contents (mass %) of Ag, Bi, Cu and In in the solder material are denoted by [Ag], [Bi], [Cu], and [In], respectively. The solder material includes In in a range of 6.0?[In]?6.8 when [Cu] falls within a range of 0<[Cu]<0.5, In in a range of 5.2+(6?(1.55×[Cu]+4.428))?[In]?6.8 when [Cu] falls within a range of 0.5?[Cu]?1.0, In in a range of 5.2?[In]?6.8 when [Cu] falls within a range of 1.0<[Cu]?1.2. A balance includes only not less than 87 mass % of Sn.
    Type: Application
    Filed: November 23, 2014
    Publication date: May 28, 2015
    Inventors: AKIO FURUSAWA, KIYOHIRO HINE, MASATO MORI, TAICHI NAKAMURA
  • Patent number: 9005751
    Abstract: Fibers containing nano-sized diamond and platinum nanocolloid, and bedding formed thereby.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: April 14, 2015
    Assignees: Venex Co., Ltd, Vision Development Co., Ltd
    Inventors: Tadamasa Fujimura, Taichi Nakamura, Shigeru Shiozaki
  • Patent number: 8957521
    Abstract: A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: February 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Taichi Nakamura, Hidetoshi Kitaura
  • Patent number: 8810035
    Abstract: A bonding structure body in which a semiconductor element and an electrode are bonded via a solder material, wherein a part that allows bonding has a first intermetallic compound layer that has been formed on the electrode side, a second intermetallic compound layer that has been formed on the semiconductor element side, and a third layer that is constituted by a phase containing Sn and a sticks-like intermetallic compound part, which is sandwiched between the two layers of the first intermetallic compound layer and the second intermetallic compound layer, and the sticks-like intermetallic compound part is interlayer-bonded to both of the first intermetallic compound layer and the second intermetallic compound layer.
    Type: Grant
    Filed: October 17, 2011
    Date of Patent: August 19, 2014
    Assignee: Panasonic Corporation
    Inventors: Taichi Nakamura, Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Yukihiro Ishimaru
  • Publication number: 20140103531
    Abstract: A bonded structure 106 includes a semiconductor element 102 bonded to a Cu electrode 103 with a bonding material 104 predominantly composed of Bi, wherein the semiconductor element 102 and the Cu electrode 103 are bonded to each other via a laminated body 209a that progressively increases a Young's modulus from the bonding material 104 to a bonded material (the semiconductor element 102 and the Cu electrode 103), achieving stress relaxation against a thermal stress generated in a temperature cycle during the use of a power semiconductor module.
    Type: Application
    Filed: May 22, 2012
    Publication date: April 17, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Taichi Nakamura, Hidetoshi Kitaura, Akihiro Yoshizawa
  • Patent number: 8691377
    Abstract: A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal having a higher melting point than the first metal and joining the electrode surface processing layer and the semiconductor element, the first metal containing particles of the second metal inside the first metal. The composition ratio of the second metal is higher than the first metal in a region of the solder material corresponding to the center portion of the semiconductor element, and the composition ratio of the second metal is at least 83.8 atomic percent in the region corresponding to the center portion.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: April 8, 2014
    Assignee: Panasonic Corporation
    Inventors: Taichi Nakamura, Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Takahiro Matsuo
  • Publication number: 20140048942
    Abstract: A mounted structure includes an electrode of a substrate, an electrode of a semiconductor element, and a mounted layers for bonding the electrode of the substrate and the electrode of the semiconductor element, and the mounted layers includes: a first intermetallic compound layer containing a CuSn-based intermetallic compound; a Bi layer; a second intermetallic compound layer containing a CuSn-based intermetallic compound; a Cu layer; and a third intermetallic compound layer containing a CuSn-based intermetallic compound, and the above layers are sequentially arranged from the electrode of the substrate toward the electrode of the semiconductor element to configure the mounted layers.
    Type: Application
    Filed: December 26, 2012
    Publication date: February 20, 2014
    Inventors: Taichi Nakamura, Hidetoshi Kitaura
  • Patent number: 8598464
    Abstract: A solder material includes 1.0-4.0% by weight of Ag, 4.0-6.0% by weight of In, 0.1-1.0% by weight of Bi, 1% by weight or less (excluding 0% by weight) of a sum of one or more elements selected from the group consisting of Cu, Ni, Co, Fe and Sb, and a remainder of Sn. When a copper-containing electrode part of an electronic component is connected to a copper-containing electrode land of a substrate by using this solder material, a part having an excellent stress relaxation property can be formed in the solder-connecting part and a Cu—Sn intermetallic compound can be rapidly grown from the electrode land and the electrode part to form a strong blocking structure.
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: December 3, 2013
    Assignee: Panasonic Corporation
    Inventors: Shigeaki Sakatani, Akio Furusawa, Kenichiro Suetsugu, Taichi Nakamura
  • Publication number: 20130241069
    Abstract: A bonding structure body in which a semiconductor element and an electrode are bonded via a solder material, wherein a part that allows bonding has a first intermetallic compound layer that has been formed on the electrode side, a second intermetallic compound layer that has been formed on the semiconductor element side, and a third layer that is constituted by a phase containing Sn and a sticks-like intermetallic compound part, which is sandwiched between the two layers of the first intermetallic compound layer and the second intermetallic compound layer, and the sticks-like intermetallic compound part is interlayer-bonded to both of the first intermetallic compound layer and the second intermetallic compound layer.
    Type: Application
    Filed: October 17, 2011
    Publication date: September 19, 2013
    Applicant: Panasonic Corporation
    Inventors: Taichi Nakamura, Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Yukihiro Ishimaru
  • Patent number: 8480806
    Abstract: A bonding structure according to the present invention includes: a ceramic member including a hole; a terminal embedded in the ceramic member and including an exposed surface exposed to a bottom portion of the hole; a brazed bond layer formed in contact with the exposed surface of the terminal; and a connecting member inserted in the hole, and bonded to the terminal via the brazed bond layer. An inner diameter of the hole is larger than an outer diameter of the connecting member. A clearance is formed between the hole and the connecting member when the connecting member is inserted in the hole. A braze pool space is formed in a surface of the hole and has a substantially semicircular shape in a cross-sectional plane. The braze pool space is partially filled with a braze material.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 9, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Taichi Nakamura, Hiroshi Takebayashi, Tomoyuki Fujii
  • Patent number: 8421246
    Abstract: A joint structure joins an electronic element 12 included in an electronic component to an electrode 14 included in that electronic component. The joint structure includes a solder layer, which contains 0.2 to 6% by weight of copper, 0.02 to 0.2% by weight of germanium and 93.8 to 99.78% by weight of bismuth, a nickel layer provided between the solder layer and the electrode, and a barrier layer provided between the nickel layer and the solder layer. Here, the barrier layer is formed so as to have an average thickness of from 0.5 to 4.5 ?m after the electronic element and the electrode are joined by the solder layer.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: April 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Akio Furusawa, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
  • Patent number: 8414704
    Abstract: The present invention relates to a bonding structure, including: a ceramic member including a hole; a terminal embedded in the ceramic member, an exposed surface exposed to a bottom portion of the hole, and made of a refractory metal having a thermal expansion coefficient substantially equal to a thermal expansion coefficient of the ceramic member; a brazed bond layer including a first tantalum layer in contact with the exposed surface of the terminal, a gold layer formed on the first tantalum layer, and a second tantalum layer formed on the gold layer; and a connecting member inserted in the hole, bonded to the terminal via the brazed bond layer, and made of a refractory metal having a thermal expansion coefficient substantially equal to the thermal expansion coefficient of the ceramic member.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: April 9, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Tomoyuki Fujii, Taichi Nakamura, Hiroshi Takebayashi
  • Patent number: 8348698
    Abstract: Male terminals are respectively provided in terminal attachment portions formed on a flange unit. Female terminals and grommets are provided for a harness. A seal lip portion to be fitted into each of the terminal attachment portions is formed on each of the grommets. In the cylindrical terminal attachment portions the male terminals are individually accommodated while being electrically insulated from each other. The terminal attachment portions are arranged alternately in two rows so that a line segment obtained by connecting the respective centers of openings of the terminal attachment portions is a polygonal line. The openings are arranged to form the Olympic symbol. At a fore-end of each of the terminal attachment portions, slits are provided. Owing to the slits, the opening is likely to be enlarged when the rubber grommet is inserted therethrough. As a result, the placement of the rubber grommet is facilitated.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: January 8, 2013
    Assignees: Mitsuba Corporation, Honda Motor Co., Ltd.
    Inventors: Bunji Homma, Takao Ikarugi, Taichi Nakamura, Yasunori Fukushima, Takeshi Yanagisawa, Masayuki Toriyama, Naoyuki Yamate
  • Patent number: 8338966
    Abstract: The present invention provides a semiconductor component having a joint structure including a semiconductor device, an electrode disposed opposite the semiconductor device, and a joining material which contains Bi as main component and connects the semiconductor device to the electrode. Since the joining material contains a carbon compound, joint failure due to the difference in linear expansion coefficient between the semiconductor device and the electrode can be reduced compared with conventional materials. The joining material which contains Bi as main component enables provision of a joint structure in which a semiconductor device and an electrode are joined by a joint more reliable than a conventional joint.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: December 25, 2012
    Assignee: Panasonic Corporation
    Inventors: Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Taichi Nakamura, Takahiro Matsuo
  • Patent number: 8268718
    Abstract: A manufacturing method for a bonded structure, in which a semiconductor device is bonded to an electrode by a bonding portion, the method including: first mounting a solder ball, in which a surface of a Bi ball is coated with Ni plating, on the electrode that is heated to a temperature equal to or more than a melting point of Bi; second pressing the solder ball against the heated electrode, cracking the Ni plating, spreading molten Bi on a surface of the heated electrode, and forming a bonding material containing Bi-based intermetallic compound of Bi and Ni; and third mounting the semiconductor device on the bonding material.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: September 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Taichi Nakamura, Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Takahiro Matsuo
  • Publication number: 20120153461
    Abstract: A semiconductor component of the present invention includes a semiconductor element and a joining layer formed on one surface of the semiconductor element and consisting of a joining material containing Bi as an essential ingredient, and projecting sections are formed on a surface of the joining layer on a side opposite to a surface in contact with the semiconductor element. By joining the semiconductor component to an electrode arranged so as to face the joining layer, the generation of a void can be suppressed.
    Type: Application
    Filed: July 20, 2010
    Publication date: June 21, 2012
    Applicant: Panasonic Corporation
    Inventors: Hidetoshi Kitaura, Akio Furusawa, Shigeaki Sakatani, Taichi Nakamura, Takahiro Matsuo
  • Patent number: 8193629
    Abstract: A bonding structure including: a ceramic member made of aluminum nitride and including a hole; a terminal embedded in the ceramic member, exposed to a bottom surface of the hole, and made of molybdenum; a brazed bond layer consisting of gold (Au) only; and a connecting member inserted in the hole, bonded to the terminal via the brazed bond layer, and made of molybdenum.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: June 5, 2012
    Assignee: NGK Insulators, Ltd.
    Inventors: Hiroshi Takebayashi, Taichi Nakamura, Tomoyuki Fujii
  • Publication number: 20120018890
    Abstract: A semiconductor device of the present invention includes a supporting board, an electrode surface processing layer formed on the supporting board, a semiconductor element, and a solder material containing a first metal composed mainly of bismuth and a second metal having a higher melting point than the first metal and joining the electrode surface processing layer and the semiconductor element, the first metal containing particles of the second metal inside the first metal. The composition ratio of the second metal is higher than the first metal in a region of the solder material corresponding to the center portion of the semiconductor element, and the composition ratio of the second metal is at least 83.8 atomic percent in the region corresponding to the center portion.
    Type: Application
    Filed: April 22, 2010
    Publication date: January 26, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Taichi Nakamura, Akio Furusawa, Shigeaki Sakatani, Hidetoshi Kitaura, Takahiro Matsuo