Patents by Inventor Taihei SHIDO
Taihei SHIDO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240110967Abstract: An evaluation circuit, a semiconductor device using the evaluation circuit, and an evaluation method using the evaluation circuit are provided to correctly measure the voltage values of individual transistors, while ensuring that there are fewer than four types of measured voltage values. The evaluation circuit includes a first switch element and a second switch element. The first switch element is disposed between a drain of the transistor and a first drain power supply. The second switch element is connected in parallel to the first switch element and disposed between the drain and a second drain power supply. A source of the transistor is electrically connected to A source power supply. A voltage applied to the second drain power supply is equal to a voltage applied to the source power supply.Type: ApplicationFiled: July 11, 2023Publication date: April 4, 2024Applicant: Winbond Electronics Corp.Inventor: Taihei SHIDO
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Publication number: 20230114844Abstract: A synchronization circuit, a semiconductor storage device, and a synchronization method provided herein, which are capable of performing synchronization on a small circuit scale, includes: a first delay circuit delaying a input synchronization signal by a first predetermined time to generate a first delay synchronization signal; a second delay circuit delaying the first delay synchronization signal by a second predetermined time to generate a second delay synchronization signal; a first synchronization circuit outputting a first output data generated by synchronizing the input data with the input synchronization signal; a second synchronization circuit outputting a second output data generated by synchronizing the input data with the first delay synchronization signal; and a resynchronization circuit resynchronizing the input data with the second delay synchronization signal to update the first output data to the first synchronization circuit when the first output data is inconsistent with the second output dType: ApplicationFiled: September 27, 2022Publication date: April 13, 2023Applicant: Winbond Electronics Corp.Inventor: Taihei SHIDO
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Patent number: 11309843Abstract: An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.Type: GrantFiled: June 7, 2021Date of Patent: April 19, 2022Assignee: Winbond Electronics Corp.Inventor: Taihei Shido
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Publication number: 20210399687Abstract: An input receiver includes a first current source circuit, a second current source circuit, a first rail-to-rail amplifier circuit, a first inverter circuit, and a second inverter circuit. The first current source circuit adjusts an operating current flowing through a first node according to a first bias signal. The second current source circuit adjusts a ground current flowing through a second node according to a second bias signal. The first rail-to-rail amplifier circuit and the first inverter circuit are connected in parallel between the first node and the second node. The first rail-to-rail amplifier circuit receives an input signal and compares the input signal with a reference voltage and accordingly outputs an amplified signal. The second inverter circuit is coupled between an operating voltage and a ground voltage. The second inverter circuit generates an output signal according to an inverted signal outputted by the first inverter circuit.Type: ApplicationFiled: June 7, 2021Publication date: December 23, 2021Applicant: Winbond Electronics Corp.Inventor: Taihei Shido
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Patent number: 11012056Abstract: A ring oscillator including a plurality of flip-flops is provided. The flip-flops are connected in a ring. The flip-flops are configured to start to oscillate according to a start signal to generate an output signal, and stop oscillating according to a stop signal to stop generating the output signal. When the stop signal changes from a first level to a second level, the output signal becomes floating. In addition, a time measuring circuit including the foregoing ring oscillator is also provided.Type: GrantFiled: April 24, 2020Date of Patent: May 18, 2021Assignee: Winbond Electronics Corp.Inventor: Taihei Shido
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Patent number: 10943625Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: GrantFiled: December 19, 2019Date of Patent: March 9, 2021Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
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Publication number: 20200395922Abstract: A ring oscillator including a plurality of flip-flops is provided. The flip-flops are connected in a ring. The flip-flops are configured to start to oscillate according to a start signal to generate an output signal, and stop oscillating according to a stop signal to stop generating the output signal. When the stop signal changes from a first level to a second level, the output signal becomes floating. In addition, a time measuring circuit including the foregoing ring oscillator is also provided.Type: ApplicationFiled: April 24, 2020Publication date: December 17, 2020Applicant: Winbond Electronics Corp.Inventor: Taihei Shido
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Patent number: 10854310Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: GrantFiled: June 10, 2019Date of Patent: December 1, 2020Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
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Patent number: 10777234Abstract: An off-chip driver including a first driving circuit is provided. The first driving circuit is used to adjust a slew rate of the off-chip driver. The first driving circuit includes a first pre-driver, a switch string, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch string is configured to perform a voltage division operation in cooperation with the first pre-driver on a power supply voltage according to the read signal, so as to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.Type: GrantFiled: August 29, 2018Date of Patent: September 15, 2020Assignee: Winbond Electronics Corp.Inventor: Taihei Shido
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Publication number: 20200126603Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: ApplicationFiled: December 19, 2019Publication date: April 23, 2020Applicant: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
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Publication number: 20200075060Abstract: An off-chip driver including a first driving circuit is provided. The first driving circuit is used to adjust a slew rate of the off-chip driver. The first driving circuit includes a first pre-driver, a switch string, and a first output stage. The first pre-driver receives a read signal and a first pre-driver control signal. The switch string is configured to perform a voltage division operation in cooperation with the first pre-driver on a power supply voltage according to the read signal, so as to generate a first output stage control signal. The first output stage generates a data signal according to the first output stage control signal.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Applicant: Winbond Electronics Corp.Inventor: Taihei Shido
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Patent number: 10553263Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: GrantFiled: December 19, 2018Date of Patent: February 4, 2020Assignee: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
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Patent number: 10468114Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: GrantFiled: June 20, 2018Date of Patent: November 5, 2019Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
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Publication number: 20190295679Abstract: Apparatuses and methods for an interface chip that interfaces with chips are described. An example apparatus includes: first terminals; circuit groups, each of the circuit groups including circuit blocks being configured to electrically couple to the first terminals; a control circuit that selects one of the circuit groups and electrically couple the first terminals to the circuit blocks of the one of the circuit groups; terminal groups, each of the terminal groups including second terminals, each of the terminal groups being provided correspondingly to each of the circuit groups, the second terminals of each of the terminal groups being smaller in number than the circuit blocks of a corresponding one of the circuit groups; and a remapping circuit that couples the second terminals of each of the terminal groups to selected ones of the circuit blocks of the corresponding one of the circuit groups.Type: ApplicationFiled: June 10, 2019Publication date: September 26, 2019Applicant: Micron Technology, Inc.Inventors: Chiaki Dono, Taihei Shido, Yuki Ebihara
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Patent number: 10424354Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.Type: GrantFiled: April 10, 2019Date of Patent: September 24, 2019Assignee: Micron Technology, Inc.Inventor: Taihei Shido
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Publication number: 20190237116Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.Type: ApplicationFiled: April 10, 2019Publication date: August 1, 2019Applicant: MICRON TECHNOLOGY, INC.Inventor: TAIHEI SHIDO
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Patent number: 10338997Abstract: An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.Type: GrantFiled: May 17, 2018Date of Patent: July 2, 2019Assignee: Micron Technology, Inc.Inventors: Chiaki Dono, Seiichi Maruno, Taihei Shido, Toshio Ninomiya, Chikara Kondo
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Patent number: 10304505Abstract: Apparatuses and methods including an interface die that interfaces with dice through memory channels are described. An example apparatus includes a first die. The first die receives a first command including first command information and second command information provided after the first command information. The first die changes an order of providing the first command information and the second command information and provides a second command to a second die, the second command including the second command information and the first command information provided after the second command information in the changed order. The first command information is related to a command function and the second command information is related to a destination of the command function.Type: GrantFiled: September 17, 2018Date of Patent: May 28, 2019Assignee: Micron Technology, Inc.Inventor: Taihei Shido
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Publication number: 20190122708Abstract: Apparatuses and methods for transmitting data between a plurality of chips are described.Type: ApplicationFiled: December 19, 2018Publication date: April 25, 2019Applicant: Micron Technology, Inc.Inventors: Chikara Kondo, Tomoyuki Shibata, Chiaki Dono, Seiji Narui, Minehiko Uehara, Taihei Shido, Homare Sato
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Patent number: 10255963Abstract: Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.Type: GrantFiled: May 14, 2018Date of Patent: April 9, 2019Assignee: Micron Technology, Inc.Inventor: Taihei Shido