Abstract: Provided is an power and communications network convergence system including wireless base stations, and DC grid groups, each grid group belonging to a cell. Each grid in the grid group has a DC line to which devices including a power generator and a power-storage are connected, and performs, based on state-information on each device, first control for reducing power fluctuations in the line. A first grid belonging to a cell performs, based on state-information on each grid, second control for interchanging power with a second grid belonging to the cell. If a power situation of a first grid group belonging to a first cell and a power-situation of a second grid group belonging to a second cell satisfy a preset condition, the first grid group performs third control for interchanging power with the second grid group.

Abstract: A network system includes a network architecture including: a network layer configured to define an entirety of an electric power network constituted from electric power grids; a local network layer configured to define a local network corresponding to electric power grid groups and forming a part of the electric power network; a grid layer configured to define the electric power grids; a physical layer configured to define constituent elements included in the electric power grids; a first layer configured to define the information communication network that is associated with the network layer; a second layer configured to define the information communication network that is associated with the local network layer; a third layer configured to define the information communication network that is associated with the grid layer; and space, a fourth layer configured to define the information communication network that is associated with the physical layer.

Abstract: A power system includes: a direct-current bus to which a power generation device and a plurality of power devices are connected; and a plurality of battery devices connected at predetermined intervals from one end of the direct-current bus to another end and configured to supply and receive power to and from the direct-current bus.

Abstract: A network system includes: a wireless base station configured to relay communication performed by wireless terminals; distributed antennas each being configured to be connected to the wireless base station and form a cell that enables communication with the wireless terminals; direct-current grids each being arranged in a predetermined form in a communication area formed by the cells and configured to interchange power with power devices connected to the subject direct-current grid; a power gate arranged between the direct-current grids located adjacent to each other and configured to interchange power between the adjacent direct-current grids; and a control device configured to control the power gate based on information acquired from the power devices via the distributed antennas. The power devices connected to the direct-current grids are configured to perform communication with the control device via the distributed antennas that form the communication area including the direct-current grids.

Abstract: Provided is an power and communications network convergence system including wireless base stations, and DC grid groups, each grid group belonging to a cell. Each grid in the grid group has a DC line to which devices including a power generator and a power storage are connected, and performs, based on state information on each device, first control for reducing power fluctuations in the line. A first grid belonging to a cell performs, based on state information on each grid, second control for interchanging power with a second grid belonging to the cell. If a power situation of a first grid group belonging to a first cell and a power situation of a second grid group belonging to a second cell satisfy a preset condition, the first grid group performs third control for interchanging power with the second grid group.

Abstract: The purpose of the present invention is to improve the efficiency of conversion between terahertz electromagnetic wave energy and direct current energy via plasma waves in a terahertz electromagnetic wave conversion device with a field effect transistor structure. This invention has an HEMT structure having a substrate, an electron transit layer, an electron supply layer, a source and a drain, and includes a first and second group of gates. The gate length of each finger of the first group of gates is narrower than the gate length of each finger of the second group of gates, and each finger of each group of gates is disposed between the source and the drain on the same cycle. A first and second distance from each finger of the first group of gates to two fingers of the second group of gates adjacent to each finger are unequal lengths.

Abstract: The purpose of the present invention is to improve the efficiency of conversion between terahertz electromagnetic wave energy and direct current energy via plasma waves in a terahertz electromagnetic wave conversion device with a field effect transistor structure. This invention has an HEMT structure having a substrate, an electron transit layer, an electron supply layer, a source and a drain, and includes a first and second group of gates. The gate length of each finger of the first group of gates is narrower than the gate length of each finger of the second group of gates, and each finger of each group of gates is disposed between the source and the drain on the same cycle. A first and second distance from each finger of the first group of gates to two fingers of the second group of gates adjacent to each finger are unequal lengths.

Abstract: Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low power consumption type logical circuit. The complementary logical gate includes an electron running layer formed by grapheme without using an n-channel FET or a p-channel FET, has the ambipolar characteristic, and uses only two FET having different threshold values, i.e., a first FET and a second FET. The first FET has a gate electrode short-circuited to a gate electrode of the second FET so as to constitute an input terminal. The first FET has a source electrode set to a low potential. The first FET has a drain electrode connected to a source electrode of the second FET so as to constitute an output terminal. The second FET has a drain electrode set to a high potential.

Abstract: The disclosed field-effect transistor has a graphene channel, and does not exhibit ambipolar properties. Specifically, the field-effect transistor has a semi-conducting substrate; a channel including a graphene layer disposed on the aforementioned semiconductor substrate; a source electrode and drain electrode comprising a metal; and a gate electrode. The aforementioned channel and the aforementioned source and drain electrodes comprising a metal are connected via a semiconductor layer.

Abstract: Provided is a complementary logical gate device represented by a silicon CMOS logical circuit among semiconductor integrated logical circuits which can effectively solve the problem of the speed performance limit of an ultra-large scale integration and an ultra-low power consumption type logical circuit. The complementary logical gate includes an electron running layer formed by grapheme without using an n-channel FET or a p-channel FET, has the ambipolar characteristic, and uses only two FET having different threshold values, i.e., a first FET and a second FET. The first FET has a gate electrode short-circuited to a gate electrode of the second FET so as to constitute an input terminal. The first FET has a source electrode set to a low potential. The first FET has a drain electrode connected to a source electrode of the second FET so as to constitute an output terminal. The second FET has a drain electrode set to a high potential.

Abstract: The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor bulk layer by a semiconductor heterojunction structure, source and drain electrodes electrically connected to two opposed sides of the two-dimensional electron layer, a double gate electrode grating which is provided in the vicinity of and parallel to the upper surface of the two-dimensional electron layer and for which two different dc bias potentials can be alternately set, and a transparent metal mirror provided in contact with the lower surface of the semiconductor bulk layer, formed into a film shape, functioning as a reflecting mirror in the terahertz band, and being transparent in the light wave band.

Abstract: The present invention improves the efficiency of conversion from a non-radiation two-dimensional electron plasmon wave into a radiation electromagnetic wave, and realizes a wide-band characteristic. A terahertz electromagnetic wave radiation element of the present invention comprises a semiinsulating semiconductor bulk layer, a two-dimensional electron layer formed directly above the semiconductor bulk layer by a semiconductor heterojunction structure, source and drain electrodes electrically connected to two opposed sides of the two-dimensional electron layer, a double gate electrode grating which is provided in the vicinity of and parallel to the upper surface of the two-dimensional electron layer and for which two different dc bias potentials can be alternately set, and a transparent metal mirror provided in contact with the lower surface of the semiconductor bulk layer, formed into a film shape, functioning as a reflecting mirror in the terahertz band, and being transparent in the light wave band.

Abstract: By measuring the waveform of the reflected wave obtained by transmitting a pulse to an open-ended transmission line, a transfer function of the transmission line with respect to the incident wave is computed as a result of the measurement. Then, the waveform of the output wave at the output end or the open end of the transmission line is estimated in response to an individual input signal by using the transfer function computed. The transmission delay time of the transmission line is obtained by computing the time difference between the transient timing of the estimated waveform of the output wave and the transient timing of the waveform of the input signal.

Abstract: Calibration of timing errors of each pin electronics unit is carried out by a main controller and a plurality of controllers, each assigned to each pin electronics unit or to each block including a plurality of pin electronics units. A reference timing signal is simultaneously distributed to each pin electronics unit or block, so that the timing error calibration is executed in parallel among the pin electronics units or the blocks.