Patents by Inventor Taiki Kimura
Taiki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105420Abstract: A data generation apparatus of one embodiment includes a processing unit, an evaluation unit, and a conversion unit. The processing unit designs, through optical proximity correction based on a target pattern formed on a substrate using the photomask, a mask pattern corresponding to the target pattern and including a plurality of rectangular regions. The evaluation unit evaluates the mask pattern using a cost function having, as a parameter, a jog length indicating a length of each of the rectangular regions included in the mask pattern in a first direction. The conversion unit converts mask pattern data indicating the mask pattern with an evaluation that meets a predetermined condition to drawing data corresponding to a variable shaped beam drawing process.Type: ApplicationFiled: June 9, 2023Publication date: March 28, 2024Applicant: Kioxia CorporationInventors: Katsuyoshi KODERA, Shoji MIMOTOGI, Shunko MAGOSHI, Ryuji OGAWA, Taiki KIMURA
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Publication number: 20230089403Abstract: According to one embodiment, a mask design method includes the following configuration. The method includes setting evaluation points on a circuit pattern created based on design data, setting a parameter that defines a shape of the mask pattern on the mask pattern corresponding to the circuit pattern and calculating an optical image intensity on the evaluation points set on the circuit pattern based on the mask pattern and the parameter. The method includes calculating an evaluation value relating to the optical image intensity by an objective function based on the optical image intensity and optimizing the parameter using a value of a partial differential for the parameter in the objective function to minimize the evaluation value calculated by the objective function.Type: ApplicationFiled: February 10, 2022Publication date: March 23, 2023Applicant: Kioxia CorporationInventors: Taiki KIMURA, Tetsuaki MATSUNAWA
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Patent number: 11526975Abstract: According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.Type: GrantFiled: September 4, 2019Date of Patent: December 13, 2022Assignee: KIOXIA CORPORATIONInventors: Yuki Watanabe, Taiki Kimura, Kazufumi Shiozawa, Kouichi Nakayama
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Patent number: 11373899Abstract: According to the present embodiment, the pattern generation device includes a misalignment value calculation unit configured to acquire a layout information, calculate a layout function from the layout information, and calculate a misalignment value by a convolution of the layout function and an integral kernel having a predetermined parameter, and a pattern correction unit configured to correct a pattern to generate a modified layout information using a calculated result by the misalignment value calculation unit, and output the modified layout information.Type: GrantFiled: March 4, 2020Date of Patent: June 28, 2022Assignee: Kioxia CorporationInventors: Taiki Kimura, Tetsuaki Matsunawa
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Patent number: 11373018Abstract: According to one embodiment, a method of displaying model includes: sampling a pattern to acquire an attention point; calculating a spatial or planar distribution that indicates any one of a design density, a lithography target density, a mask transmittance, or an optical image intensity at N points (N being an integer equal to or greater than 1) on the pattern including the attention point; calculating a threshold for the pattern; estimating, based on the distribution and the threshold, N elements respectively corresponding to the N points as a model; and displaying the estimated model.Type: GrantFiled: September 6, 2018Date of Patent: June 28, 2022Assignee: KIOXIA CORPORATIONInventor: Taiki Kimura
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Publication number: 20200388528Abstract: According to the present embodiment, the pattern generation device includes a misalignment value calculation unit configured to acquire a layout information, calculate a layout function from the layout information, and calculate a misalignment value by a convolution of the layout function and an integral kernel having a predetermined parameter, and a pattern correction unit configured to correct a pattern to generate a modified layout information using a calculated result by the misalignment value calculation unit, and output the modified layout information.Type: ApplicationFiled: March 4, 2020Publication date: December 10, 2020Applicant: Kioxia CorporationInventors: Taiki KIMURA, Tetsuaki MATSUNAWA
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Publication number: 20200118261Abstract: According to one embodiment, a method for displaying an index value in generation of a mask pattern verification model includes: calculating a first index value using a plurality of images; estimating a model on the basis of the first index value and pattern information; calculating a second index value using the model; and displaying at least one of the first index value and the second index value.Type: ApplicationFiled: September 4, 2019Publication date: April 16, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuki WATANABE, Taiki KIMURA, Kazufumi SHIOZAWA, Kouichi NAKAYAMA
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Publication number: 20190228119Abstract: According to one embodiment, a method of displaying model includes: sampling a pattern to acquire an attention point; calculating a spatial or planar distribution that indicates any one of a design density, a lithography target density, a mask transmittance, or an optical image intensity at N points (N being an integer equal to or greater than 1) on the pattern including the attention point; calculating a threshold for the pattern; estimating, based on the distribution and the threshold, N elements respectively corresponding to the N points as a model; and displaying the estimated model.Type: ApplicationFiled: September 6, 2018Publication date: July 25, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventor: Taiki KIMURA
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Patent number: 9576100Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.Type: GrantFiled: December 22, 2014Date of Patent: February 21, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
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Publication number: 20160059518Abstract: A magnet is applicable to a movable electrical machine and includes a plurality of resin protrusions at a plurality of positions on a surface of the magnet.Type: ApplicationFiled: August 26, 2015Publication date: March 3, 2016Applicant: KABUSHIKI KAISHA YASKAWA DENKIInventors: Masahito FUKUNAGA, Kanta Yamaguchi, Taiki Kimura
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Publication number: 20160026079Abstract: A mask pattern correcting method according to an embodiment is a correcting method of a mask pattern to be used in a semiconductor device manufacturing process. In the correcting method, a plurality of kernels calculated based on an optical system of an exposure tool is prepared. Weight coefficients for weighting the kernels, respectively, to be used when the kernels are synthesized, are calculated. The kernels are synthesized using the calculated weight coefficients. The mask pattern is corrected using the synthesized kernels.Type: ApplicationFiled: January 29, 2015Publication date: January 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Taiki KIMURA, Toshiya Kotani, Masanori Takahashi
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Publication number: 20150113485Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.Type: ApplicationFiled: December 22, 2014Publication date: April 23, 2015Inventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
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Patent number: 8984454Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.Type: GrantFiled: March 13, 2013Date of Patent: March 17, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Seiro Miyoshi, Taiki Kimura, Hiromitsu Mashita, Fumiharu Nakajima, Tetsuaki Matsunawa, Toshiya Kotani, Chikaaki Kodama
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Publication number: 20140059502Abstract: According to an embodiment, a pattern data generation method is provided. In the pattern data generation method, when a resist on a substrate is exposed using a mask, an optical image at a designated resist film thickness position is calculated using a mask pattern. Feature quantity related to a shape of a resist pattern at the resist film thickness position is extracted, based on the optical image. Also, whether the resist pattern is failed is determined, based on the feature quantity, and pattern data of a mask pattern determined as failed is corrected.Type: ApplicationFiled: March 13, 2013Publication date: February 27, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Seiro MIYOSHI, Taiki KIMURA, Hiromitsu MASHITA, Fumiharu NAKAJIMA, Tetsuaki MATSUNAWA, Toshiya KOTANI, Chikaaki KODAMA
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Patent number: 7583131Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.Type: GrantFiled: February 27, 2008Date of Patent: September 1, 2009Assignees: Sanyo Electric Co., Ltd., Sanyo Semiconductor Co., Ltd.Inventors: Taiki Kimura, Kensuke Goto
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Publication number: 20080218250Abstract: In a charge pump circuit provided with a positive electric potential generating charge pump circuit that generates a positive electric potential and a negative electric potential generating charge pump circuit that generates a negative electric potential, a parasitic bipolar transistor is prevented from turning on so that the charge pump circuit performs normal voltage boosting operation. First, the negative electric potential generating charge pump circuit is put into operation to generate ?VDD as an output electric potential LV. Since the output electric potential LV is applied to a P-type semiconductor substrate, an electric potential of the P-type semiconductor substrate becomes ?VDD. After that, the positive electric potential generating charge pump circuit is put into operation while the negative electric potential generating charge pump circuit continues its operation.Type: ApplicationFiled: February 27, 2008Publication date: September 11, 2008Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.Inventors: Taiki KIMURA, Kensuke GOTO