Patents by Inventor Taiki Uemura
Taiki Uemura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240079687Abstract: Provided are a power generation method and a power generating element capable of obtaining an electromotive force by utilizing humidity variation in an environment and having excellent operation stability. An aqueous solution of an ionic compound having deliquescence is separated by an ion permeable membrane, electrodes are inserted into the aqueous solution on both sides of the ion permeable membrane, one is blocked from outside air and sealed, and the other is connected to the outside air, and a difference in ion concentration derived from the ionic compound in the aqueous solution is generated across the ion permeable membrane due to a change in humidity in the outside air to generate an electromotive force between the electrodes.Type: ApplicationFiled: October 13, 2021Publication date: March 7, 2024Applicant: National Institute of Advanced Industrial Science and TechnologyInventors: Yusuke Komazaki, Kenji Kanazawa, Taiki Nobeshima, Hirotada Hirama, Yuichi Watanabe, Sei Uemura
-
Patent number: 11837323Abstract: A device including: defining unit to define lattice space that is collection of lattices compound groups are sequentially arranged; limiting unit to, in the case where any of the compound groups is arranged in any of the lattices of lattice space followed by arranging next compound group in the lattice space, generate limited lattice space created by eliminating, from the lattice space, undesirable regions for the next compound group to be arranged; and assigning unit to assign bit to each of lattice points, to which the compound groups can be arranged, in the limited lattice space; and an arithmetic unit configured to perform ground state search on Ising model obtained through conversion based on restriction conditions related to each lattice point according to simulated annealing, to calculate minimum energy of the Ising model, wherein the device is for searching compound in which the compound groups are linked with one another.Type: GrantFiled: August 7, 2019Date of Patent: December 5, 2023Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Takayuki Shibasaki
-
Patent number: 11537916Abstract: An optimization apparatus includes a memory; and a processor coupled to the memory and the processor configured to: compute a local solution for a combinatorial optimization problem based on a first evaluation function representing the combinatorial optimization problem, select a state variable group targeted by partial problems from the plurality of state variables based on a first state variable whose value at the local solution is a predetermined value among the plurality of state variables included in the first evaluation function, a weight coefficient representing a magnitude of an interaction between the plurality of state variables held in a storage unit, and input selection region information, search a ground state for a second evaluation function representing the partial problems for the selected state variable group, and generate a whole solution by updating the local solution based on the partial solutions acquired by the ground state search.Type: GrantFiled: June 11, 2020Date of Patent: December 27, 2022Assignee: FUJITSU LIMITEDInventors: Toshiyuki Miyazawa, Takayuki Shibasaki, Taiki Uemura
-
Publication number: 20220310211Abstract: A non-transitory computer-readable storage medium storing an information processing program that causes a processor included in an information processing apparatus that analyzes a first molecule different from all of a plurality of molecules based on characteristic data of each of the plurality of molecules to execute a process, the process includes specifying a structure descriptor that is an index based on each of structures of the plurality of molecules; and generating a model used to analyze the first molecule based on the structure descriptor and a similarity between each of the structures of the plurality of molecules.Type: ApplicationFiled: December 15, 2021Publication date: September 29, 2022Applicant: FUJITSU LIMITEDInventors: Hideyuki Jippo, Akito MARUO, Taiki Uemura
-
Patent number: 11114418Abstract: An electronic device includes: a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; and a second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space.Type: GrantFiled: April 24, 2019Date of Patent: September 7, 2021Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Taiji Sakai, Seiki Sakuyama
-
Publication number: 20200410372Abstract: An optimization apparatus includes a memory; and a processor coupled to the memory and the processor configured to: compute a local solution for a combinatorial optimization problem based on a first evaluation function representing the combinatorial optimization problem, select a state variable group targeted by partial problems from the plurality of state variables based on a first state variable whose value at the local solution is a predetermined value among the plurality of state variables included in the first evaluation function, a weight coefficient representing a magnitude of an interaction between the plurality of state variables held in a storage unit, and input selection region information, search a ground state for a second evaluation function representing the partial problems for the selected state variable group, and generate a whole solution by updating the local solution based on the partial solutions acquired by the ground state search.Type: ApplicationFiled: June 11, 2020Publication date: December 31, 2020Applicant: FUJITSU LIMITEDInventors: Toshiyuki Miyazawa, Takayuki Shibasaki, Taiki Uemura
-
Publication number: 20200135295Abstract: A device including: a defining unit to define lattice space that is collection of lattices where compound groups are sequentially arranged; a limiting unit; an assigning unit; an arithmetic unit; a judging unit; and a controlling unit to cause the limiting unit to execute expansion of the limited lattice space, the assigning unit to execute assignment of the bits to the lattice points included in the limited lattice space after the expansion, and the arithmetic unit to execute calculation of the minimum energy, in case where the judging unit judges any of the compound groups assigned to the lattice points is arranged on the outermost edge, wherein the device is device for searching the compound, in which the compound groups are linked with one another.Type: ApplicationFiled: September 11, 2019Publication date: April 30, 2020Applicant: FUJITSU LIMITEDInventors: Takayuki Shibasaki, Taiki Uemura
-
Publication number: 20200082904Abstract: A device including: defining unit to define lattice space that is collection of lattices compound groups are sequentially arranged; limiting unit to, in the case where any of the compound groups is arranged in any of the lattices of lattice space followed by arranging next compound group in the lattice space, generate limited lattice space created by eliminating, from the lattice space, undesirable regions for the next compound group to be arranged; and assigning unit to assign bit to each of lattice points, to which the compound groups can be arranged, in the limited lattice space; and an arithmetic unit configured to perform ground state search on Ising model obtained through conversion based on restriction conditions related to each lattice point according to simulated annealing, to calculate minimum energy of the Ising model, wherein the device is for searching compound in which the compound groups are linked with one another.Type: ApplicationFiled: August 7, 2019Publication date: March 12, 2020Applicant: FUJITSU LIMITEDInventors: Taiki Uemura, Takayuki Shibasaki
-
Patent number: 10422832Abstract: A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.Type: GrantFiled: May 9, 2017Date of Patent: September 24, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Taiki Uemura
-
Publication number: 20190252357Abstract: An electronic device includes: a first layer that includes first electronic components in a group and has a first through space between adjacent ones of the first electronic components; and a second layer that is stacked over the first layer and includes second electronic components which are coupled to the first electronic components and a second through space between adjacent ones of the second electronic components, the second through space being partially overlapping with the first through space.Type: ApplicationFiled: April 24, 2019Publication date: August 15, 2019Applicant: FUJITSU LIMITEDInventors: Taiki Uemura, Taiji Sakai, Seiki Sakuyama
-
Patent number: 10383229Abstract: An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.Type: GrantFiled: March 9, 2018Date of Patent: August 13, 2019Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Taiji Sakai, Hideki Kitada
-
Patent number: 10167537Abstract: An electronic apparatus includes: a first electronic component including a first electrode; solder on the first electrode; and a phase containing In, Ag, and Cu, the phase being dispersed and included in the solder. And a method for manufacturing an electronic apparatus, the method includes: forming solder on a first electrode of a first component, the solder including a phase containing In, Ag, and Cu, the phase being dispersed in the solder.Type: GrantFiled: December 7, 2015Date of Patent: January 1, 2019Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Kozo Shimizu, Seiki Sakuyama
-
Publication number: 20180279476Abstract: An electronic apparatus includes a first circuit board, a stacked circuit that is provided on the first circuit board through first coupling terminals and has a structure in which arithmetic elements and memory elements are stacked through inter-element coupling terminals and to which a signal is inputted from the first circuit board, and a second circuit board that is provided on the stacked circuit through second coupling terminals and to which a result of processing is outputted from the stacked circuit, wherein a number of the first coupling terminals and a number of the second coupling terminals are smaller than that of the inter-element coupling terminals.Type: ApplicationFiled: March 9, 2018Publication date: September 27, 2018Applicant: FUJITSU LIMITEDInventors: Taiki UEMURA, Taiji SAKAI, Hideki KITADA
-
Publication number: 20180088176Abstract: A sequential circuit includes a data input terminal, a data path, and a redundant feedback loop. The data input terminal receives input data. The data path is connected to the data input terminal and transmits the input data to a data output terminal based on a first clock signal and a second clock signal. The redundant feedback loop is connected to the first data path and stores first data based on at least one of the first or second clock signals when the first data is equal to second data. The first data corresponds to the input data. The second clock signal is a delayed signal of the first clock signal. The second data is delayed data of the first data.Type: ApplicationFiled: May 9, 2017Publication date: March 29, 2018Inventor: Taiki UEMURA
-
Patent number: 9831199Abstract: An electronic device includes a first electronic part, a second electronic part opposite the first electronic part, and a bonding portion between the first electronic part and the second electronic part. The bonding portion contains a solder containing a substance whose crystal structure reversibly changes in temperature rise and fall processes which accompany the operation of the electronic device or electronic equipment including the electronic device. A change in the crystal structure of the substance contained in the solder promotes recovery and recrystallization of the solder in the temperature rise and fall processes which accompany the operation of the electronic device or the electronic equipment. As a result, the coarsening of crystal grains in the solder is suppressed.Type: GrantFiled: September 26, 2016Date of Patent: November 28, 2017Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Seiki Sakuyama
-
Patent number: 9831210Abstract: An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu6Sn5, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.Type: GrantFiled: November 28, 2016Date of Patent: November 28, 2017Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Seiki Sakuyama
-
Publication number: 20170207186Abstract: An electronic device includes an electrode including Cu, a solder including Sn and provided above the electrode, and a joining layer including In and Ag and provided along a boundary between the electrode and the solder. The joining layer including In and Ag prevents Cu—Sn alloy, such as Cu6 Sn5, from being formed at the boundary between the electrode and the solder, and prevents generation of voids and cracks resulting from the Cu—Sn alloy. The electrode and the solder are joined with sufficient strength by the joining layer.Type: ApplicationFiled: November 28, 2016Publication date: July 20, 2017Applicant: FUJITSU LIMITEDInventors: Taiki Uemura, Seiki Sakuyama
-
Publication number: 20170125366Abstract: An electronic device includes a first electronic part, a second electronic part opposite the first electronic part, and a bonding portion between the first electronic part and the second electronic part. The bonding portion contains a solder containing a substance whose crystal structure reversibly changes in temperature rise and fall processes which accompany the operation of the electronic device or electronic equipment including the electronic device. A change in the crystal structure of the substance contained in the solder promotes recovery and recrystallization of the solder in the temperature rise and fall processes which accompany the operation of the electronic device or the electronic equipment. As a result, the coarsening of crystal grains in the solder is suppressed.Type: ApplicationFiled: September 26, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventors: Taiki Uemura, Seiki Sakuyama
-
Patent number: 9640508Abstract: An electrical apparatus includes a first electrical component; a second electrical component; and an In—Sn—Ag alloy connecting the first electrical component and the second electrical component, the In—Sn—Ag alloy containing AgIn2 and Ag2In, a Ag2In content being lower than a AgIn2 content.Type: GrantFiled: October 16, 2015Date of Patent: May 2, 2017Assignee: FUJITSU LIMITEDInventors: Taiki Uemura, Kozo Shimizu, Seiki Sakuyama
-
Publication number: 20160233181Abstract: An electronic device includes a first electronic component including a first electrode, a solder provided above the first electrode, and a first bonding layer provided between the first electrode and the solder and containing Pd, Ag, and In. In another aspect of the invention, a method for manufacturing an electronic device, the method includes providing a solder containing In and Ag above a layer containing Pd and provided above an electrode of an electronic component; and melting the solder by heating to form a bonding layer containing Pd, Ag, and In between the electrode and the solder.Type: ApplicationFiled: January 13, 2016Publication date: August 11, 2016Applicant: FUJITSU LIMITEDInventors: Taiki Uemura, Seiki Sakuyama, Kozo Shimizu