Patents by Inventor Taiki YAMAMOTO
Taiki YAMAMOTO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11981523Abstract: A sheet conveying device includes a sheet stacker, an air blower, and a guide. The sheet stacker stacks sheets. The air blower blows air to the sheets. The guide faces an uppermost sheet on the sheet stacker. A set height of a contact portion of the guide to contact the uppermost sheet is changeable.Type: GrantFiled: April 11, 2022Date of Patent: May 14, 2024Assignee: Ricoh Company, Ltd.Inventors: Taiki Yamamoto, Takahiro Ogino, Takashi Ebihara, Satoshi Kohara, Kazuhiro Shimojima
-
Publication number: 20240102688Abstract: An indoor unit included in an air conditioner that includes an outdoor unit includes a power receiving circuit (PR2), a low-frequency transmission and reception circuit as a first reception circuit, a high-frequency transmission and reception circuit as a transmission and reception circuit, and an inner-controller. The low-frequency transmission and reception circuit receives a current signal transmitted from an outdoor unit by using a current loop formed by a power line included in power supply wiring. For a first communication state in which physical connection between with the outdoor unit is recognized and a second communication state in which communication for operation of the air conditioner is performed between with the outdoor unit, the inner-controller selects use of the low-frequency transmission and reception circuit and the high-frequency transmission and reception circuit in the first communication state and the second communication state.Type: ApplicationFiled: November 30, 2023Publication date: March 28, 2024Applicant: DAIKIN INDUSTRIES, LTD.Inventors: Ryosuke YAMAMOTO, Yohei KOYAMA, Youta KATOU, Kazuaki ANDO, Taiki KOGAWA, Shin HIGASHIYAMA, Kosuke HOTTA, Shinichi ISHIZEKI, Toshiaki KUMATA
-
Motion state monitoring system, training support system, motion state monitoring method, and program
Patent number: 11925458Abstract: A motion state monitoring system, a training support system, a motion state monitoring method, and a program capable of suitably managing measurement results according to an attaching direction of a sensor are provided. A motion state monitoring system according to the present disclosure monitors a motion state of a target part of a subject's body. The motion state monitoring system includes an acquisition unit, an attaching direction detection unit, and a control processing unit. The acquisition unit acquires sensing information of a sensor attached to the target part. The attaching direction detection unit detects an attaching direction of the sensor. The control processing unit outputs information related to the sensing information in association with the attaching direction.Type: GrantFiled: August 13, 2021Date of Patent: March 12, 2024Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Makoto Kobayashi, Toru Miyagawa, Issei Nakashima, Keisuke Suga, Masayuki Imaida, Manabu Yamamoto, Yohei Otaka, Masaki Katoh, Asuka Hirano, Taiki Yoshida -
Publication number: 20230266689Abstract: The present invention relates to a binder resin composition capable of giving a toner remarkably excellent in fusing property on polypropylene films, and to a toner for developing electrostatic images that contains the binder resin composition.Type: ApplicationFiled: April 6, 2023Publication date: August 24, 2023Applicant: KAO CORPORATIONInventors: Yuki WAKABAYASHI, Taiki YAMAMOTO
-
Patent number: 11711474Abstract: A reading device and an image forming apparatus. The reading device includes a reader disposed at a scanning position, the reader being configured to read an image formed on a surface of a sheet, a movement mechanism to move the reader between the scanning position and a separated position away from the scanning position, and a reference plate disposed at a first position facing a reading face of the reader, the reference plate being configured to obtain a reference value to be used when the reader reads the image. In the reading device, the reference plate rotates around an axis from a second position facing a side of the reader to the first position or from the first position to the second position in conjunction with movement of the reader from the scanning position to the separated position by the movement mechanism The image forming apparatus includes the reading device.Type: GrantFiled: June 24, 2022Date of Patent: July 25, 2023Assignee: RICOH COMPANY, LTD.Inventors: Taiki Yamamoto, Yusuke Tokunaga, Yuichiro Maeyama, Kiyoshi Hata
-
Patent number: 11652150Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.Type: GrantFiled: August 6, 2018Date of Patent: May 16, 2023Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Kuniyuki Kakushima, Takuya Hoshii, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Taiki Yamamoto
-
Publication number: 20230030207Abstract: A reading device and an image forming apparatus. The reading device includes a reader disposed at a scanning position, the reader being configured to read an image formed on a surface of a sheet, a movement mechanism to move the reader between the scanning position and a separated position away from the scanning position, and a reference plate disposed at a first position facing a reading face of the reader, the reference plate being configured to obtain a reference value to be used when the reader reads the image. In the reading device, the reference plate rotates around an axis from a second position facing a side of the reader to the first position or from the first position to the second position in conjunction with movement of the reader from the scanning position to the separated position by the movement mechanism The image forming apparatus includes the reading device.Type: ApplicationFiled: June 24, 2022Publication date: February 2, 2023Inventors: Taiki YAMAMOTO, Yusuke TOKUNAGA, Yuichiro MAEYAMA, Kiyoshi HATA
-
Patent number: 11513149Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.Type: GrantFiled: August 6, 2018Date of Patent: November 29, 2022Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Kuniyuki Kakushima, Takuya Hoshii, Hitoshi Wakabayashi, Kazuo Tsutsui, Hiroshi Iwai, Taiki Yamamoto
-
Publication number: 20220324670Abstract: A sheet conveying device includes a sheet stacker, an air blower, and a guide. The sheet stacker stacks sheets. The air blower blows air to the sheets. The guide faces an uppermost sheet on the sheet stacker.Type: ApplicationFiled: April 11, 2022Publication date: October 13, 2022Applicant: Ricoh Company, Ltd.Inventors: Taiki YAMAMOTO, Takahiro OGINO, Takashi EBIHARA, Satoshi KOHARA, Kazuhiro SHIMOJIMA
-
Publication number: 20210242017Abstract: One embodiment of the present invention provides a semiconductor wafer 1 which is provided with: a substrate 10 that is mainly composed of Si, a buffer layer 11 that is formed on the substrate 10 and comprises an AlN layer 11a as the lowermost layer; and a nitride semiconductor layer 12 that is formed on the buffer layer 11 and contains Ga. This semiconductor wafer 1 is configured such that the pit density of the upper surface of the AlN layer 11a is more than 0 but less than 2.4×1010 cm?2.Type: ApplicationFiled: February 6, 2019Publication date: August 5, 2021Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki YAMAMOTO, Keitaro IKEJIRI
-
Publication number: 20210173318Abstract: The present invention relates to a liquid developer containing toner particles containing a colorant and a binder resin containing a polyester resin; and an insulating liquid, wherein the polyester resin includes a constituent unit derived from an alcohol component and a constituent unit derived from a carboxylic acid component, and the toner particles contain an acid-modified product A of a polymer of an ?-olefin having 3 or more and 18 or less carbon atoms.Type: ApplicationFiled: December 26, 2018Publication date: June 10, 2021Applicant: KAO CORPORATIONInventors: Taiki YAMAMOTO, Yuki WAKABAYASHI
-
Patent number: 11031249Abstract: A semiconductor wafer is provided, which includes a wafer; a nitride crystal layer formed of one or more crystal layers of group III nitride; and a cap layer; the wafer, the nitride crystal layer and the cap layer are positioned in an order of the wafer, the nitride crystal layer and the cap layer, and the cap layer is a silicon nitride layer having crystallinity and has a thickness of 5 nm or more. Also, a semiconductor wafer is provided, where a layer that is of the nitride crystal layer and that is in contact with the cap layer, and a layer near the layer function as active layers of a field-effect transistor, the cap layer is a silicon nitride layer having crystallinity and a thickness that is equal to or larger than a thickness in which a gate of the field-effect transistor can be embedded.Type: GrantFiled: June 26, 2019Date of Patent: June 8, 2021Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki Yamamoto, Takenori Osada
-
Patent number: 11011630Abstract: A semiconductor wafer is provided, which has a silicon wafer, a reaction suppressing layer, a stress generating layer and an active layer, the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer being disposed in an order of the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer, where the reaction suppressing layer is a nitride crystal layer that suppresses reaction between silicon atoms and group-III atoms, the stress generating layer is a nitride crystal layer that generates compressive stress, the active layer is a nitride crystal layer in which an electronic device is formed, and the semiconductor wafer further has, between the silicon wafer and the reaction suppressing layer, a SiAlN layer having silicon atoms, aluminum atoms and nitrogen atoms as main constituent atoms.Type: GrantFiled: May 29, 2019Date of Patent: May 18, 2021Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki Yamamoto, Takenori Osada
-
Publication number: 20210141317Abstract: The present invention relates to a binder resin composition capable of giving a toner remarkably excellent in fusing property on polypropylene films, and to a toner for developing electrostatic images that contains the binder resin composition.Type: ApplicationFiled: June 22, 2018Publication date: May 13, 2021Applicant: KAO CORPORATIONInventors: Yuki WAKABAYASHI, Taiki YAMAMOTO
-
Patent number: 10763332Abstract: Provided is a semiconductor wafer in which a nitride crystal layer on a silicon wafer includes a reaction suppressing layer to suppress reaction between a silicon atom and a Group-III atom, a stress generating layer to generate compressive stress and an active layer in which an electronic element is to be formed, the reaction suppressing layer, the stress generating layer and the active layer are arranged in an order of the reaction suppressing layer, the stress generating layer and the active layer with the reaction suppressing layer being positioned the closest to the silicon wafer, and the stress generating layer includes a first crystal layer having a bulk crystal lattice constant of al and a second crystal layer in contact with a surface of the first crystal layer that faces the active layer, where the second crystal layer has a bulk crystal lattice constant of a2 (a1<a2).Type: GrantFiled: May 4, 2017Date of Patent: September 1, 2020Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Hisashi Yamada, Taiki Yamamoto, Kenji Kasahara
-
Publication number: 20200225276Abstract: One embodiment of the present invention provides a method for evaluating the electrical defect density of a semiconductor layer, which comprises: a step for measuring an electric current by applying a voltage to a semiconductor element 1 which comprises a GaN layer 12 that serves as a semiconductor layer; and a step for deriving the electrical defect density in the GaN layer 12 with use of the measured electric current value.Type: ApplicationFiled: August 6, 2018Publication date: July 16, 2020Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Kuniyuki KAKUSHIMA, Takuya HOSHII, Hitoshi WAKABAYASHI, Kazuo TSUTSUI, Hiroshi IWAI, Taiki YAMAMOTO
-
Publication number: 20200203493Abstract: Provided are a charge trap evaluation method and semiconductor device including, in an embodiment, a step for applying an initialization voltage that has the same sign as a threshold voltage and is greater than or equal to the threshold voltage between the source electrode 15 and drain electrode 16 of a semiconductor device 1 having an HEMT structure and the substrate 10 of the semiconductor device 1 and initializing a trap state by forcing out trapped charge from a trap level and a step for monitoring the current flowing between the source electrode 15 and drain electrode 16 after the trap state initialization and evaluating at least one from among charge trapping, current collapse, and charge release.Type: ApplicationFiled: August 6, 2018Publication date: June 25, 2020Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Kuniyuki KAKUSHIMA, Takuya HOSHII, Hitoshi WAKABAYASHI, Kazuo TSUTSUI, Hiroshi IWAI, Taiki YAMAMOTO
-
Patent number: 10642181Abstract: A liquid developer containing toner particles containing a resin binder containing a polyester-based resin and a colorant, a dispersant, and an insulating liquid, wherein the dispersant contains a dispersant X having an adsorbing group having a nitrogen-containing group represented by the formula (I): wherein each of R1, R2, and R3, which may be identical or different, is an alkylene group having 1 or more carbon atoms and 22 or less carbon atoms, an alkenylene group having 2 or more carbon atoms and 22 or less carbon atoms, an alkynylene group having 2 or more carbon atoms and 22 or less carbon atoms, or an arylene group having 6 or more carbon atoms and 22 or less carbon atoms, and a dispersing group having a hydrocarbon group having a number-average molecular weight of 500 or more, and wherein the dispersant X has a mass ratio of the adsorbing group to the dispersing group (adsorbing group/dispersing group) of 1/99 or more and 42/58 or less, and a proportion of the dispersing group having a hydrocarbonType: GrantFiled: August 25, 2017Date of Patent: May 5, 2020Assignee: Kao CorporationInventors: Nobumichi Kamiyoshi, Tatsuya Yamada, Taiki Yamamoto, Kunihiro Kano
-
Publication number: 20190318934Abstract: A semiconductor wafer is provided, which includes a wafer; a nitride crystal layer formed of one or more crystal layers of group III nitride; and a cap layer, the wafer, the nitride crystal layer and the cap layer are positioned in an order of the wafer, the nitride crystal layer and the cap layer, and the cap layer is a silicon nitride layer having crystallinity and has a thickness of 5 nm or more. Also, a semiconductor wafer is provided, where a layer that is of the nitride crystal layer and that is in contact with the cap layer, and a layer near the layer function as active layers of a field-effect transistor, the cap layer is a silicon nitride layer having crystallinity and has a thickness that is equal to or larger than a thickness in which a gate of the field-effect transistor is to be embedded.Type: ApplicationFiled: June 26, 2019Publication date: October 17, 2019Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki Yamamoto, Takenori Osada
-
Publication number: 20190296136Abstract: A semiconductor wafer is provided, which has a silicon wafer, a reaction suppressing layer, a stress generating layer and an active layer, the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer being disposed in an order of the silicon wafer, the reaction suppressing layer, the stress generating layer and the active layer, where the reaction suppressing layer is a nitride crystal layer that suppresses reaction between silicon atoms and group-III atoms, the stress generating layer is a nitride crystal layer that generates compressive stress, the active layer is a nitride crystal layer in which an electronic device is formed, and the semiconductor wafer further has, between the silicon wafer and the reaction suppressing layer, a SiAlN layer having silicon atoms, aluminum atoms and nitrogen atoms as main constituent atoms.Type: ApplicationFiled: May 29, 2019Publication date: September 26, 2019Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Taiki YAMAMOTO, Takenori OSADA