Abstract: A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well.

Abstract: A method of making a high-electron mobility transistor (HEMT) includes forming an unintentionally doped gallium nitride (UID GaN) layer over a silicon substrate, a donor-supply layer over the UID GaN layer, a gate, a passivation layer over the gate and portions of the donor-supply layer, an ohmic source structure and an ohmic drain structure over the donor-supply layer and portions of the passivation layer. The source structure includes a source contact portion and an overhead portion. The overhead portion overlaps the passivation layer between the source contact portion and the gate, and may overlap a portion of the gate and a portion of the passivation layer between the gate and the drain structure.

Abstract: Among other things, an electrostatic discharge (ESD) device is provided. The ESD device comprises a dielectric isolation structure that is formed between an emitter and a collector of the ESD device. During an ESD event, current flows from the emitter, substantially under the dielectric isolation structure, to the collector, to protect associated circuitry. The dielectric isolation structure is formed to a depth that is less than a depth of at least one of the emitter or the collector, or doped regions thereof, thereby decreasing a length of a current path from the emitter to the collector, because the current is not obstructed by the dielectric isolation structure. Accordingly, the ESD device can carry higher current during the ESD event because the shorter current path has less resistance than a longer path that would otherwise be traveled if the dielectric isolation structure was not formed at the shallower depth.

Abstract: Fabrication of monolithic lattice-mismatched semiconductor heterostructures with limited area regions having upper portions substantially exhausted of threading dislocations, as well as fabrication of semiconductor devices based on such lattice-mismatched heterostructures.

Abstract: A reference voltage generator is described. The reference voltage generator includes a proportional to absolute temperature (PTAT) current source, the PTAT current source being capable of providing a first current that is proportional to a temperature. The reference voltage generator further includes a current mirror comprising a first transistor and a second transistor, the current mirror configured to generate a second current proportional to the first current, wherein a ratio of the first current to the second current is equal to a ratio of a gate width of the first transistor to a gate width of the second transistor. The reference voltage generator further includes a voltage divider, the voltage divider being capable of receiving the second current, the voltage divider capable of outputting a reference voltage, the reference voltage being substantially independent from a change of the temperature.

Abstract: A method of fabricating an integrated circuit device is provided. The method includes forming a replacement gate structure with a dummy polysilicon layer on a first surface of a substrate. The method further includes depositing a dielectric layer by a thermal process to form offset spacers on two opposing sides of the replacement gate structure, wherein the dielectric layer is deposited on the first surface and a second surface opposing the first surface of the substrate. The method further includes removing the dummy polysilicon layer from the replacement gate structure, wherein the dielectric layer on the second surface of the substrate protects the second surface of the substrate during the removing step.

Abstract: A device includes a semiconductor substrate having a front surface and a back surface opposite the front surface. An insulation region extends from the front surface into the semiconductor substrate. An inter-layer dielectric (ILD) is over the insulation region. A landing pad extends from a top surface of the ILD into the insulation region. A through-substrate via (TSV) extends from the back surface of the semiconductor substrate to the landing pad.

Abstract: A semiconductor device includes a substrate formed of a first semiconductor material; two insulators on the substrate; and a semiconductor region having a portion between the two insulators and over the substrate. The semiconductor region has a bottom surface contacting the substrate and having sloped sidewalls. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material.

Abstract: A method of forming a dielectric layer on a further layer of a semiconductor device is disclosed. The method comprises depositing a dielectric precursor compound and a further precursor compound over the further layer, the dielectric precursor compound comprising a metal ion from the group consisting of Yttrium and the Lanthanide series elements, and the further precursor compound comprising a metal ion from the group consisting of group IV and group V metals; and chemically converting the dielectric precursor compound and the further precursor compound into a dielectric compound and a further compound respectively, the further compound self-assembling during said conversion into a plurality of nanocluster nuclei within the dielectric layer formed from the first dielectric precursor compound. The nanoclusters may be dielectric or metallic in nature. Consequently, a dielectric layer is formed that has excellent charge trapping capabilities.

Abstract: A programmable transistor array circuit is disclosed comprising a semiconductor substrate; and a plurality of basic transistor units (BTUs) arranged in rows and columns of uniformly spaced cells, the BTUs further comprising PMOS transistor units (PTUs), NMOS transistor units (NTUs) and dummy transistor units (DTUs) each BTU having conductors arranged in a single direction running through the BTUs and the conductors being uniformly spaced with respect to each other. The arrangement of the BTUs is subject to restricted design rules. Logical transistor units (LTUs) are formed from the BTUs using first and second layers of metallization. Additional embodiments are disclosed incorporating the programmable transistor array circuit.

Abstract: An integrated circuit structure includes a fin field-effect transistor (FinFET) including a semiconductor fin over and adjacent to insulation regions; and a source/drain region over the insulation regions. The source/drain region includes a first and a second semiconductor region. The first semiconductor region includes silicon and an element selected from the group consisting of germanium and carbon, wherein the element has a first atomic percentage in the first semiconductor region. The first semiconductor region has an up-slant facet and a down-slant facet. The second semiconductor region includes silicon and the element. The element has a second atomic percentage lower than the first atomic percentage. The second semiconductor region has a first portion on the up-slant facet and has a first thickness. A second portion of the second semiconductor region, if any, on the down-slant facet has a second thickness smaller than the first thickness.

Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: A method including receiving layout data representing the plurality of patterns, the layout data including a plurality of layers and identifying spaces between adjacent patterns in at least one layer of the plurality of layers which violate a G0-rule, by a processor of a computer system. The method further includes determining whether each identified space is a critical G0-space, by the processor, wherein the identified space is determined to be the critical G0-space if removal of a portion of at least one of pattern merges two adjacent odd-loops of G0-spaces into a single even-loop of G0-spaces or converts one odd-loop of G0-spaces to a non-loop of G0-spaces. The method further includes receiving a modification of the at least one pattern and updating a spacing of a layer adjacent to the at least one layer based on the received modification, by the processor.

Abstract: A three dimensional (3D) stacked chip structure with chips having on-chip heat spreader and method of forming are described. A 3D stacked chip structure comprises a first die having a first substrate with a dielectric layer formed on a front surface. One or more bonding pads and a heat spreader may be simultaneously formed in the dielectric layer. The first die is bonded with corresponding bond pads on a surface of a second die to form a stacked chip structure. Heat generated in the stacked chip structure may be diffused to the edges of the stacked chip structure through the heat spreader.

Abstract: A method for forming a semiconductor device includes forming a substrate, forming a moveable member of bulk silicon and forming a first dimple structure on a first surface of the moveable member, where the first surface faces the substrate.

Abstract: A system and method for controlling a dosage profile is disclosed. An embodiment comprises separating a wafer into components of a grid array and assigning each of the grid components a desired dosage profile based upon a test to compensate for topology differences between different regions of the wafer. The desired dosages are decomposed into directional dosage components and the directional dosage components are translated into scanning velocities of the ion beam for an ion implanter. The velocities may be fed into an ion implanter to control the wafer-to-beam velocities and, thereby, control the implantation.

Abstract: An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.

Abstract: Provided is an apparatus that includes an overlay mark. The overlay mark includes a first portion that includes a plurality of first features. Each of the first features have a first dimension measured in a first direction and a second dimension measured in a second direction that is approximately perpendicular to the first direction. The second dimension is greater than the first dimension. The overlay mark also includes a second portion that includes a plurality of second features. Each of the second features have a third dimension measured in the first direction and a fourth dimension measured in the second direction. The fourth dimension is less than the third dimension. At least one of the second features is partially surrounded by the plurality of first features in both the first and second directions.

Abstract: A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

Abstract: System and method for reducing contact resistance and improving barrier properties is provided. An embodiment comprises a dielectric layer and contacts extending through the dielectric layer to connect to conductive regions. A contact barrier layer is formed between the conductive regions and the contacts by electroless plating the conductive regions after openings have been formed through the dielectric layer for the contact. The contact barrier layer is then treated to fill the grain boundary of the contact barrier layer, thereby improving the contact resistance. In another embodiment, the contact barrier layer is formed on the conductive regions by electroless plating prior to the formation of the dielectric layer.