Patents by Inventor Taiyuu Miyamoto

Taiyuu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6631467
    Abstract: A microcomputer has an internal reset signal generator for generating an internal reset signal from an external reset signal supplied via a chip reset input terminal. The internal reset signal generator includes a first two-input logic circuit that has its first gate input terminal connected to the chip reset input terminal and outputs a low-level first logic signal only when its two gate input terminals are placed at a high level. The first logic signal is inverted by an inverter and is supplied to the second gate input terminal of the first two-input logic circuit. The second gate input terminal is pulled up by a capacitor connected to a higher power supply voltage terminal. The external reset signal and the first logic signal are supplied to a second two-input logic circuit that changes the level of the reset signal only when both the inputs are at the high level.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Taiyuu Miyamoto
  • Publication number: 20020116570
    Abstract: A microcomputer having a data EEPROM and a program EEPROM, in which a predetermined lock code is written a the specific area, comprising a lock-code-decoding circuit that is connected with the data EEPROM, reads out the concerned lock code, and decodes the code; a logic circuit that performs a predetermined operation on a mode bit that was serially input from the outside, by the output of the lock-code-decoding circuit; and a mode-bit-decoding circuit that decodes the processed mode bit by receiving the output of the logic circuit, and sends the result to functional blocks, is provided; and thereby the falsification of the data of money and the program written in a nonvolatile memory can be prevented.
    Type: Application
    Filed: December 3, 2001
    Publication date: August 22, 2002
    Inventor: Taiyuu Miyamoto
  • Patent number: 6070804
    Abstract: A non-contact type IC card includes a rectifier circuit for supplying a source voltage to respective circuits of an IC card based on the strength of radio waves received from a host computer. A reference voltage generating circuit generates a reference voltage. A comparison circuit compares the source voltage with the reference voltage. A control circuit prohibits the writing of data if the source voltage becomes less than the reference voltage.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: June 6, 2000
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Taiyuu Miyamoto
  • Patent number: 5864588
    Abstract: A communications device, such as a non-contact IC card, demodulates a received carrier signal, which has been modulated with data to be transmitted thereto by changing the phase of the carrier signal intermittently according to the data, so as to extract the data from the carrier signal.
    Type: Grant
    Filed: April 23, 1996
    Date of Patent: January 26, 1999
    Assignees: Mitsubishi Electric Semiconductor Software Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventor: Taiyuu Miyamoto
  • Patent number: 5648929
    Abstract: Addresses for a plurality of consecutive logic blocks are managed by assigning the addresses to their corresponding addresses for physical blocks of a plurality of flash memory devices such that the addresses for the plurality of continuous logic blocks are respectively distributed into the plurality of flash memory devices. When block erase commands are inputted from the outside, chip enable signals are respectively transmitted to at least two of the flash memory devices in which physical blocks to be erased exist, in such a manner that a period in which at least two flash memory devices simultaneously perform block erase operations, exists.
    Type: Grant
    Filed: July 21, 1995
    Date of Patent: July 15, 1997
    Assignees: Mitsubishi Electric Semiconductor Software Co., Ltd., Mitsubishi Denki Kabushiki Kaisha
    Inventor: Taiyuu Miyamoto