Abstract: In a situation where a moving picture, representing a person playing the piano, is being displayed on a screen responsive to an animation signal, while a human voice reporting an item of news is being output responsive to an audio signal with a caption displayed on the screen as an icon image, a comparator continuously compares information such as “Next, we will have the weather forecast . . . ” contained in the voice with another information like “weather” prescribed by an operator. The moment a correspondence is found between these pieces of information, the caption, which has been displayed as an icon image, is turned into a window. In this manner, information contained in an audio signal is always monitored and when a predetermined condition is met, an icon image is changed into a window automatically and timely. Accordingly, an operator need not perform a troublesome operation of manually changing an icon image into a window.

Abstract: This invention provides a computer capable of displaying information in multiple windows and handling multiple audio signals in a manner convenient for a user. This is achieved in one embodiment of the present invention by audibly producing only one audio signal at a time, but allowing the user to monitor a second received audio signal by visually representing the second audio signal through a displayed icon. The display of the icon may vary over time, reflecting time-variable characteristics of the signal represented by the icon, thus enabling the user to monitor the audio signals that are received but not actually audibly produced. Examples of such time-variable characteristics include volume, semantics and pitch.

Abstract: An instruction address that is referred to by a microprocessor unit is inputted over an instruction address bus and is stored. While counting the number of times a clock is fed to the microprocessor unit, a comparison is made between the stored instruction address and an instruction address that the microprocessor provides onto the instruction address bus. A clock count value, obtained at the time when the aforesaid instruction addresses agree, is stored. If a stored instruction address and an instruction address on the instruction address bus agree for every stored clock count value, then the microprocessor is judged to repeatedly execute a sequence of instructions and the loop count value is incremented by one. When the loop count value exceeds a predetermined value, the microprocessor is judged to be placed in an idle state and the clock frequency is lowered.

Abstract: An image blend circuit comprising a first image memory and a second image memory output pixel data according to pixel location information containing a pixel clock signal generated by an image location information supply unit, and a counter counts. Blend ratios are read from the counter and a blend ratio buffer. A data selector selects between these blend ratios according to a control signal from an attribute buffer and applies a selected blend ratio to a pixel blend unit. The pixel blend unit, depending upon the received blend ratio, translucently synthesizes or selects pixels from the first and second image memories. In an information processor, when opening a plurality of windows on a display screen produces an overlap field between the windows, such overlapped images are translucently blended for translucent image display. Therefore, the blend ratio can be set with less write information.

Abstract: Pixel data is selected from among first and second dynamic-image memories (DI1, DI2) and a static-memory (SI). In the invention, (a) first and second window area memories (WA1, WA2) for designating shapes and sizes of windows to which video dynamic-images are assigned respectively, (b) first and second dynamic-image area memories (DA1, DA2) for designating memory locations of data stored in both the dynamic-image memories, and (c) a priority control register for designating which video dynamic-image should be displayed in front when video dynamic-images overlap with each other are provided, whereby display for every pixel is executed according to a logical AND value of read-out data from WA1 and read-out data from DA1, a logical AND value of read-out data from WA2 and read-out data from DA2, and read-out data from the priority control register.

Abstract: A data processing apparatus includes a first (k.times.m)-bit data bus wherein k is a byte count and m is a bit length of one byte, a plurality of m-bit I/O peripheral devices at least one which is connected to two or more of m-bit data buses belonging to a first group consisting of first to k-th m-bit data buses obtained by dividing the first (k.times.m)-bit data bus into the first to k-th m-bit data buses; a second (k.times.m)-bit data bus, a (k.times.m)-bit I/O central processing unit connected to the second (k.times.m)-bit data bus which is divided into (k+1)-th m-bit data buses consisting of a second group of m-bit data buses; a data path switching circuit connected between the first and second (k.times.m)-bit data buses which forms a data transmission path between an arbitrary two of said plurality of m-bit I/O peripheral devices and the CPU, and a transmission control circuit for generating control signals responsive to a demand of data transmission from said CPU.