Patents by Inventor Tak-Kei LAM

Tak-Kei LAM has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Register-transfer level signal mapping construction method, device, apparatus and storage medium
    Publication number: 20230153499
    Abstract: A register-transfer level signal mapping construction method and device, wherein the register-transfer level signal mapping construction method comprises: acquiring register-transfer level codes and netlist level codes corresponding to the register-transfer level codes; constructing a circuit according to the register-transfer level codes and the netlist level codes; separating the circuit into a plurality of modules according to syntax of the circuit in a hardware description language; determining a correspondence relationship between the plurality of modules with logic verification methods; acquiring register-transfer level signals of a mapping relationship to be established; and determining netlist level signals corresponding to the register-transfer level codes according to the correspondence relationship between the plurality of modules.
    Type: Application
    Filed: September 29, 2022
    Publication date: May 18, 2023
    Inventors: Xing WEI, Yi DIAO, Tak Kei LAM
  • Methods and apparatus for removing functional bugs and hardware trojans for integrated circuits implemented by field programmable gate array (FPGA)
    Patent number: 11409916
    Abstract: A method to transform the function of a programmable circuit (e.g. FPGA) for removing functional bugs or Hardware Trojans is provided.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 9, 2022
    Assignee: EASY-LOGIC TECHNOLOGY LTD.
    Inventors: Yu-Liang Wu, Xing Wei, Tak-Kei Lam, Yi Diao
  • Methods and Apparatus for Removing Functional Bugs and Hardware Trojans for Integrated Circuits Implemented by Field Programmable Gate Array (FPGA)
    Publication number: 20200394340
    Abstract: A method to transform the function of a programmable circuit (e.g. FPGA) for removing functional bugs or Hardware Trojans is provided.
    Type: Application
    Filed: August 28, 2020
    Publication date: December 17, 2020
    Inventors: Yu-Liang WU, Xing WEI, Tak-Kei LAM, Yi DIAO