Abstract: A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.