Abstract: A circuit includes a control circuit configured to receive a selection signal transitioning within a first voltage domain; and generate, based on the selection signal, a first control signal transitioning within a second voltage domain different from the first voltage domain. The circuit further includes a switch circuit operatively coupled to the control circuit and comprising a first header transistor coupled to a first voltage supply transitioning within the second voltage domain, and gated by the first control signal; and a second header transistor coupled to a second voltage supply transitioning within the first voltage domain, and gated by a second control signal that is logically inverse to the first control signal. The first header transistor and the second header transistor are complementarily turned on so as to provide an output voltage equal to either the first voltage supply or the second voltage supply.

Abstract: A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.

Abstract: A semiconductor memory device includes a first conductor that extends in a first direction, a second conductor that extends in a second direction, a first memory cell connected between the first conductor and the second conductor and including a phase change element, and a control circuit. The control circuit applies a first voltage across the first memory cell via the first conductor and the second conductor during a first period of time of a write operation targeted to the first memory cell, and a second voltage across the first memory cell via the first conductor and the second conductor during a second period of time of the write operation after the first period. The first voltage is an overshoot voltage. The second voltage is a preset voltage having a magnitude sufficient to place the phase change element in a molten state during the second period of time.

Abstract: A semiconductor storage device includes a memory cell having a first variable resistance element changeable from a first state to a second state at which a resistance value of the first variable resistance element is higher than that of the first variable resistance element at the first state, and a second variable resistance element connected to the first variable resistance element in series and changeable from a third state to a fourth state at which a resistance value of the second variable resistance element is higher than that of the second variable resistance element at the third state. In the memory cell, a first snapback occurs at a first threshold current and a first threshold voltage, and a second snapback occurs at a second threshold current that is greater than the first threshold current and a second threshold voltage that is greater than the first threshold voltage.

Abstract: A semiconductor memory device includes a first conductor that extends in a first direction, a second conductor that extends in a second direction, a first memory cell connected between the first conductor and the second conductor and including a phase change element, and a control circuit. The control circuit applies a first voltage across the first memory cell via the first conductor and the second conductor during a first period of time of a write operation targeted to the first memory cell, and a second voltage across the first memory cell via the first conductor and the second conductor during a second period of time of the write operation after the first period. The first voltage is an overshoot voltage. The second voltage is a preset voltage having a magnitude sufficient to place the phase change element in a molten state during the second period of time.

Abstract: A sense amplifier circuit includes first and second lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line.

Abstract: A sense amplifier circuit includes first and second signal lines and first and second inverters. Each inverter includes an input terminal, an output terminal, and a power source terminal. A second signal line potential is supplied to the first inverter input terminal. The second inverter input terminal is connected to the first inverter output terminal, and the second inverter output terminal is connected to the first inverter input terminal. A first signal line potential is supplied to the second inverter input terminal. A first switch transistor is connected to the first inverter power source terminal and has a gate connected to the second signal line. A switch second transistor is connected to the second inverter power source terminal and has a gate connected to the first signal line.

Abstract: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.

Abstract: Methods and systems for embodiments of a 9T memory cell, memory devices which utilize such 9T memory cells and the creation of embodiments of such memory devices are disclosed. More specifically, an embodiment of a 9T memory cell may comprise a 6T memory cell portion and a 3T read port. Additionally, in one embodiment, a memory which utilizes 9T memory cells may be made by from a grid comprising columns and rows of transistors formed according to a layout for 6T memory cells.

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract: A memory system including a memory array with redundant wordlines. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.

Abstract: A memory system including a memory array with redundant wordlines is disclosed. The memory system includes a memory wordline tester that determines if any of the wordlines exhibits a defect. The memory system also includes decoder redundancy logic that efficiently couples to wordline shift logic using a reduced number of control signal lines therebetween. The shift logic shifts defective wordlines to upstream wordlines in the array to bypass the defective wordlines.

Abstract: Disclosed are embodiments of a method and apparatus for avoiding cell data destruction caused by cell stability problems in static random access memory (SRAM) cells. In one embodiment, data inside of an SRAM cell is transferred to one of its bitline in advance of an actual Read/Write operation utilizing a transfer device controlled by a pre-read signal. In one embodiment, the read and write bitlines are shared and the transfer device and pr are not needed. Since the bitline voltage has already been changed to the state which reflects the cell data in advance, the memory cells remains relatively stable. By shifting the bitline voltage before the wordline is turned on, the accessed cell is relieved from the stress which would have otherwise caused cell stability problems.

Abstract: An apparatus, a method, and a computer program are provided to efficiently use a microprocessor array. Typically, microprocessor arrays can be divided into multiple subarrays. Also, in the conventional arrays, each of the subarrays were engaged when the microprocessor array is used. To alleviate the power consumed by the microprocessor arrays, row selection logic is employed to engage only specific rows of subarrays. Therefore, power consumed by unused subarrys is saved.

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract: A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.

Abstract: Systems and methods for reducing or eliminating the effect of timing variations in signals generated by devices that are subject to the history effect, wherein devices are enabled using a combination of timing signals, some of which are subject to timing variations arising from the history effect, and some of which are not. In one embodiment, a sense amplifier includes a pair of serially configured transistors that couple the sense amplifier to ground. One of the transistors is switched on/off by a clock signal that is not subject to history-effect timing variations, and the other is switched on/off by a signal that is subject to such variations. The second signal has pulses that are selectively delayed so that they will (or will not) overlap with the pulses of the clock signal in a controlled manner.

Abstract: Systems and methods for increasing the amount of current that can flow through the data line pull-down transistors in a sense amplifier by tying the bodies of these transistors to a voltage other than ground. In one embodiment, the bodies of the data line pull-down transistors in a sense amplifier are tied to the intermediate nodes on the opposing side of the sense amplifier to increase the current flow through the data line pull-down transistors, and also to reduce the voltage at the intermediate node that will be pulled low by the action of the bit line transistors. In one embodiment, the sense amplifier also includes pre-charge circuits which pre-charge the intermediate nodes to a predetermined voltage that is not reduced by the threshold voltage of the pull-down transistors.

Abstract: Systems and methods for decreasing the sensitivity of a sense amplifier to variations in the threshold voltages of the data line pull-down transistors by pre-charging the intermediate nodes of the sense amplifier to the voltages on the opposing bit lines when the sense amplifier is not enabled. In one embodiment, the intermediate nodes are coupled to the input bit lines through transistors that are switched on when the sense amplifier is not enabled and switched off when the sense amplifier is enabled. In one embodiment, the intermediate nodes are pre-charged to a predetermined voltage before being pre-charged to the voltages on the bit lines. In one embodiment, the bodies of the data line pull-down transistors may also be body-tied to the opposing intermediate nodes to increase current flow through these transistors, particularly on the side of the sense amplifier that will be pulled low when the sense amplifier is enabled.

Abstract: A method, an apparatus, and a computer program are provided to reduce the number of required latches in a deep pipeline wordline (WL) decoder. Traditionally, a signal local clock buffer (LCB) has been responsible for providing a driving signal to a WL driver. However, with this configuration, a large number of latches are utilized. To reduce this latch usage, a number of LCBs are employed, such that one latch can enable an increased number of WLs. Hence, the overall area occupied by latches is reduced and power consumption is reduced.