Abstract: A UPC circuit fault diagnosis system for diagnosing a failure in a UPC circuit controls cell traffic volume on the basis of prescribed information about cell traffic. Failure diagnosis of a UPC circuit is provided by a usage parameter determination of at least one kind of cell, using more than one system and comparing determination results. The diagnosis system has an operating UPC circuit for controlling a total of m kinds of cells, and a standby UPC circuit for controlling a total of n kinds of cells. The system also has a total of q bridge memories for keeping a chronological record of the prescribed information of arriving cells. A fault diagnosis of the bridge memories is provided by comparing the contents of the bridge memories, using more than one system.

Abstract: A method for structuring a communications network based on an asynchronous transfer mode in which communications are held with the use of cells transferred between a node on the upstream side and a node on the downstream side. The method for structuring the network includes a step for preparing a plurality of VPI conversion tables for converting VPIs of the cell input under normal communicating conditions and that of the cell input in the event of a failure and outputting the cell with the VPI converted. The prepared VPI conversion tables are reorganized for each node and the reorganized VPI conversion tables are distributed to all nodes. Then, an alternate route monitoring and switching virtual path is set up in each alternate route and a monitoring cell is periodically transmitted along the alternate route.

Abstract: In an ATM switching network, ATM (asynchronous transfer mode) self-routing switches are interconnected by facilities carrying STM-N (synchronous transport modules level N) signals. At each inlet of an ATM self-routing switch, an STM overhead is removed from each frame of an incoming STM-N signal to create a vacant interval and the frame is converted according to ATM cell format into a series of data ATM cells, and an idle ATM cell is derived from the vacant interval. A supervisory bit sequence is inserted to the payload field of the idle ATM cell to produce a supervisory ATM cell, and the data and supervisory ATM cells are sent into the ATM switch. At each outlet of the switch, the bit sequence of the supervisory ATM cell is checked to evaluate the quality of the ATM switch and a series of data ATM cells is then converted into an STM-N signal according to STM-N frame format.

Abstract: A route switching system in a communications network constituted of a transmitter and a receiver connected by a plurality of routes for switching a first route along which communication is being held by transmission of cells to a second route causing no blocking. The route switching system comprises a first switch provided in the transmitter for switching input cells from one route to another and outputting the cells, a first storage portion provided in the transmitter for storing the input cells, a second switch provided in the receiver for switching input cells from one route to another and outputting the cells, and a second storage portion provided in the receiver for storing the input cells. At the time when the route is switched over, the first switch is changed over so that the cells are transmitted through the first storage portion and, on the receiver side, the second switch is changed over so that the cells transmitted over the second route are stored into the second storage portion.

Abstract: A method includes the steps of a failure which occurs in a node or link, and b) identifying at most N (N is an integer equal to or greater than 2) nodes contained in each path affected by the occurrence of the failure. Each path is connected to a sender node which detects the failure, information is transferred to the sender node via the N nodes, and the sender node serves as a start point of each alternate path which is to be established. The method also includes the step of c) broadcasting a restoration message to links which outgo from the sender node, where the restoration message has an identifier of the sender node and identifiers of the N nodes specified for each path affected by the occurrence of the failure. The identifiers of the N nodes specified for each path being candidate nodes of an end point of each alternate path.

Abstract: An offset compensating circuit is disclosed. The offset compensating circuit is inserted in a negative feedback loop of a circuit to be compensated and includes an integration circuit. The integration circuit includes a switching means mechanism and a switched capacitor type integrator. Said switching means mechanism produces either a positive reference voltage or a negative reference voltage in accordance with the polarity of the output signal of the circuit to be compensated. The positive or negative reference voltage is applied to the switched capacitor type integrator, which produces a compensating voltage signal to be combined with the input signal of the circuit to be compensated.

Abstract: A device for discriminating between two values of a signal using DC offset compensation including an automatic gain control circuit, a peak detector circuit and a feedback path from the peak detector circuit to the input circuit of the automatic gain control circuit. The value of the feedback current is regulated so that the maximum value of one of the same polarity signals and the opposite polarity signal coincides with the minimum value of the other of the two signals.