Abstract: A pump unit for a chromatograph includes a plunger pump and an upstream check valve. The plunger pump has a pump head and pumps a mobile phase. The upstream check valve is provided upstream of the pump head. The upstream check valve includes a flow-path portion and a temperature regulator. The flow-path portion guides the mobile phase to the plunger pump. The temperature regulator regulates a temperature of the mobile phase passing through the flow-path portion.

Abstract: An automatic analyzer includes a cleaning pool, a discharge port, a waste fluid pipe, a valve, and a guiding unit. The cleaning pool is used to clean a predetermined member with a fluid. The discharge port discharges the fluid. The waste fluid pipe connects the cleaning pool and the discharge port. The valve is disposed to the waste fluid pipe. The guiding unit guides a cleaning fluid to the cleaning pool via the waste fluid pipe.

Abstract: An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Abstract: An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

Abstract: An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Abstract: An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

Abstract: An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

Abstract: A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers.

Abstract: In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the plurality of slave ports, an address phase that issues an address and a command and a data phase that issues write data are separated, and an address phase of next transaction can be issued before the data phase is completed. This improves performance of a system, in which a plurality of master modules and slave modules are connected through the bus.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Abstract: An image processing apparatus includes a production unit that can produce data by putting original image data into a first region and copy-forgery-inhibited-pattern image data into a second region, and a processing unit that can perform predetermined processing to the original image data put in the first region. The image processing apparatus further includes a composite image data producing unit that can produce composite image data based on both of the original image data to which the predetermined processing is performed and the copy-forgery-inhibited-pattern image data put in the second region of the data.

Abstract: A memory system includes a memory and a plurality of memory controllers for accessing the memory. One of the plurality of memory controllers synchronizes the one of the plurality of memory controllers with the plurality of memory controllers.

Abstract: An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Abstract: An image input/output control apparatus includes a control device for controlling input/output of image data with an external apparatus, plural image processing devices for performing predetermined image processes to the image data, and plural data transfer devices for connecting each of the plural image processing devices and the control device like a ring and performing data transfer among them. The plural image processing devices and the control device are composed respectively on different units, whereby the structure of the apparatus can be easily changed, and a decrease in processing speed due to the competition for buses can be reduced without increasing the number of parts necessary for bus control.

Abstract: A P bus from a CPU, an MC bus from a system memory, an IO bus to which an input/output device has been connected, and a G bus for transferring image data of a scanner/printer controller are connected to a system bus bridge (SBB). The SBB connects any of the P bus, G bus and IO bus as a master and any of the MC bus and IO bus as a slave in dependence upon a request from a master. At this time the P bus and IO bus can be connected in parallel with the G bus and MC bus. As a result, access to the memory by the scanner/printer controller can be carried out in parallel with use of the input/output device by the CPU. This makes it possible to process a large quantity of data, such as image data, efficiently.

Abstract: The present invention efficiently compresses image data, and stores and manages the compressed data. Image data is compressed in tile unit having predetermined pixels and data packing is performed. The compressed data is compared with compressed data of a preceding packet. If these compressed data are different, the packet data is stored in a memory, and an entry address of the compressed data is stored in a packet table. Meanwhile, if the compressed data is equal to the compressed data of the preceding packet, the compressed data is not stored, but an entry address of the compressed data of the preceding packet is stored in a record of interest in the packet table, and a flag indicative of repetition of the preceding address is set in the packet of interest.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: In plural master apparatus connected to a bus, a master apparatus issues, to an arbiter, a request signal requesting the use of the bus after a lapse of a predetermined interval when the use of the bus becomes necessary, while another master apparatus issues, to the arbiter, a request signal requesting the use of the bus immediately when the use of the bus becomes necessary. The arbiter grants a right to use the bus by equally handling the request signals from the master apparatus. Also there is prepared a signal indicating a traffic in the bus, and the request signal is issued after the lapse of the interval in case of a high traffic but it is issued immediately in case of a low traffic. It is thus possible to adjust the practical priority of the but use right in detail or to dynamically change such priority by the presence or absence of such interval or a length thereof.

Abstract: In a bus, which is provided with a switch having a plurality of master ports and a plurality of slave ports and can connect each of the plurality of master ports to an arbitrary port of the plurality of slave ports, an address phase that issues an address and a command and a data phase that issues write data are separated, and an address phase of next transaction can be issued before the data phase is completed. This improves performance of a system, in which a plurality of master modules and slave modules are connected through the bus.