Patents by Inventor Takafumi Konno

Takafumi Konno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020192872
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: August 8, 2002
    Publication date: December 19, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020192871
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≧1.2 t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Application
    Filed: July 26, 2002
    Publication date: December 19, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20020182776
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: July 12, 2002
    Publication date: December 5, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6476466
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: November 5, 2002
    Assignee: Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020137262
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Application
    Filed: May 23, 2002
    Publication date: September 26, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20020137261
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads. In a molding member-sealed semiconductor device wherein the semiconductor chip is fixed to the heat radiation plate, the tip thickness t′ of the inner leads is made less than the thickness t of the other portions of the inner leads secured to the heat radiation plate.
    Type: Application
    Filed: May 23, 2002
    Publication date: September 26, 2002
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Patent number: 6448111
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: September 10, 2002
    Assignees: Hitachi Hokkai Semiconductor, Ltd., Hitachi, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6437428
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: August 20, 2002
    Assignee: Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020079579
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: January 31, 2002
    Publication date: June 27, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Publication number: 20020070462
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: January 31, 2002
    Publication date: June 13, 2002
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6396142
    Abstract: In a semiconductor device having a heat radiation plate, the tips of inner leads connected to a semiconductor chip have a lead width w and a lead thickness t, the width being less than the thickness. The inner leads are secured to the heat radiation plate. Fastening the inner leads to the heat radiation plate supports the latter and eliminates the need for suspending leads. A lead pitch p, the lead width w and lead thickness t of the inner lead tips connected to the semiconductor chip have the relations of w<t and p≦1.2t, with the inner leads secured to the heat radiation plate. The heat radiation plate has slits made therein to form radially shaped heat propagation paths between a semiconductor chip mounting area and the inner leads.
    Type: Grant
    Filed: August 6, 1999
    Date of Patent: May 28, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Fujio Ito, Hiroaki Tanaka, Hiromichi Suzuki, Tokuji Toida, Takafumi Konno, Kunihiro Tsubosaki, Shigeki Tanaka, Kazunari Suzuki, Akihiko Kameoka
  • Publication number: 20020050642
    Abstract: A semiconductor device is disclosed, comprising a tape substrate which supports a semiconductor chip, an insulating adhesive layer disposed between the semiconductor chip and the tape substrate, an insulating sheet member laminated to the insulating adhesive layer and formed harder than the insulating adhesive layer, wires for connecting pads on the semiconductor chip with connecting terminals on the tape substrate, a sealing portion formed by sealing the semiconductor chip with resin, and plural solder balls provided on a back of the tape substrate. A die bonding layer for fixing the semiconductor chip thereto is composed of an insulating adhesive layer and the insulating sheet member laminated thereto. The die bonding layer is formed thick by such a multi-layer structure, whereby the resin balance of the surface and back of the semiconductor chip is improved to prevent warping of a package and improve the mounting temperature cyclicity and reflow characteristic.
    Type: Application
    Filed: October 18, 2001
    Publication date: May 2, 2002
    Inventors: Riyouichi Oota, Tsugihiko Hirano, Atsushi Fujisawa, Takafumi Konno
  • Publication number: 20010050419
    Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.
    Type: Application
    Filed: July 16, 2001
    Publication date: December 13, 2001
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
  • Publication number: 20010015489
    Abstract: In a method of forming a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Application
    Filed: April 26, 2001
    Publication date: August 23, 2001
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani
  • Patent number: 6265762
    Abstract: There is provided a semiconductor chip mounting area for mounting a semiconductor chip, and the points of the inner leads are made to come closer to the semiconductor chip mounting area by arranging the points of the inner leads at equal intervals over the whole periphery of the semiconductor chip mounting area. The points of the inner leads are arranged along the whole periphery of the semiconductor chip mounting area, and the lead pitch at the points of the inner leads corresponding to a corner portion of the semiconductor chip mounting area is made wider than the lead pitch of the other inner lead points.
    Type: Grant
    Filed: March 18, 1997
    Date of Patent: July 24, 2001
    Assignees: Hitachi, LTD, Hitachi Hoakki Semiconductor, LTD
    Inventors: Shigeki Tanaka, Atsushi Fujisawa, Souichi Nagano, Tsugihiko Hirano, Ryouichi Oota, Takafumi Konno, Kenichi Tatebe, Toshiaki Okamoto
  • Patent number: 6232650
    Abstract: In a ball grid array type semiconductor package, a semiconductor chip is mounted through an adhesive material on a surface of a flexible film substrate. Plural bump electrodes are arranged in an array on the opposite side of said substrate and the semiconductor chip is sealed by a resin. In this regard, an insulation layer is formed to cover an electric conductor layer pattern formed on the surface of the substrate, and the semiconductor chip is mounted through an adhesive material on the insulation layer. The insulation layer is divided into a plural number of parts that are mutually discontinuous in the area under the semiconductor chip. By this divided insulation layer, a short circuit between the semiconductor chip and the electric conductor layer pattern is prevented and a deformation of the substrate that comprises the flexible films is suppressed.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: May 15, 2001
    Assignees: Hitachi, Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Atsushi Fujisawa, Takafumi Konno, Shingo Ohsaka, Ryo Haruta, Masahiro Ichitani