Abstract: A wiring board 10 comprises a wiring board main body 21 having a dielectric layer 25 that is the first dielectric layer, an electronic component attaching pad 24 having a connection surface 24A with which an electronic component 11 is connected, and disposed inside the dielectric layer 25, a dielectric layer 31 that is the second dielectric layer laminated on the dielectric layer 25, and the via holes 27 and 33 and a wiring pattern 28 provided on the dielectric layers 25 and 31 and electrically connected with the electronic component attaching pad 24, wherein a warp reduction member 22 for reducing a warp of the wiring board main body 21 is disposed inside the dielectric layer 25.

Abstract: A wiring board 10 comprises a wiring board main body 21 having a dielectric layer 25 that is the first dielectric layer, an electronic component attaching pad 24 having a connection surface 24A with which an electronic component 11 is connected, and disposed inside the dielectric layer 25, a dielectric layer 31 that is the second dielectric layer laminated on the dielectric layer 25, and the via holes 27 and 33 and a wiring pattern 28 provided on the dielectric layers 25 and 31 and electrically connected with the electronic component attaching pad 24, wherein a warp reduction member 22 for reducing a warp of the wiring board main body 21 is disposed inside the dielectric layer 25.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: A wiring board 10 comprises a wiring board main body 21 having a dielectric layer 25 that is the first dielectric layer, an electronic component attaching pad 24 having a connection surface 24A with which an electronic component 11 is connected, and disposed inside the dielectric layer 25, a dielectric layer 31 that is the second dielectric layer laminated on the dielectric layer 25, and the via holes 27 and 33 and a wiring pattern 28 provided on the dielectric layers 25 and 31 and electrically connected with the electronic component attaching pad 24, wherein a warp reduction member 22 for reducing a warp of the wiring board main body 21 is disposed inside the dielectric layer 25.

Abstract: A thickness of the portion, which is placed between an electronic component mounting pad and a first wiring, of a first insulating layer (insulating layer in which electronic component mounting pads are placed) is set to be smaller than a thickness of the portion, which is placed between the first wiring and a second wiring, of a second insulating layer.

Abstract: A semiconductor package includes: a build-up wiring layer including a metal wiring layer and an insulation resin layer; and a low thermal expansion material layer having a coefficient of thermal expansion closer to that of a semiconductor chip mounted on the build-up wiring layer as compared with the insulation resin layer of the build-up wiring layer, the low thermal expansion material layer being bonded to an entire region of a rear surface of the build-up wiring layer corresponding to a region of a front surface of the build-up wiring layer on which the semiconductor chip is mounted.

Abstract: A coaxial line assembly in a package which houses a high frequency element. The assembly includes a metal wall having a hole extending through the metal wall. The metal wall has a step at substantially an intermediate portion of the hole to define a smaller diameter, inner hole portion opened to the inside of the package and a larger diameter, outer hole portion opened to the outside of the package. A lead for transmitting a high frequency signal passes through the hole and is hermetically sealed in the outer hole portion by glass filled in the outer hole portion. A sealing plate closes an opening of the inner hole portion at the step, the lead extending through the sealing plate. The sealing plate is made of a dielectric material having a dielectric constant near to that of the glass and a melting point higher than that of the glass.

Abstract: A process for making a metal wall enclosure of a package for housing an electronic element. An elongated strip, to be formed as the metal sidewall of the enclosure, and a bottom plate, for closing an open end of the metal sidewall, are formed from a sheet of metal stock. At least one aperture is selectively provided in at least one of the bottom plate and the planar metal strip. The strip is prepared for folding, such as by transverse grooves formed in the strip along predetermined fold lines corresponding to corners of the metal sidewall, to facilitate folding of the strip into the desired configuration of the metal sidewall and with the opposite ends of the strip, as folded to form the metal sidewall, in abutting relationship.