Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform an error correction on data read from a memory region of the non-volatile memory, and set a value of a parameter corresponding to a number of parity bits to be added to write data to be written into the memory region based on a number of data bits corrected in the error correction of the read data in a case where the error correction is successful.

Abstract: A memory system includes a nonvolatile memory device and a controller circuit. The nonvolatile memory device includes a plurality of physical blocks, each including a storage area which is accessible in units of pages. The controller circuit is configured to control reading and writing of data which are performed on the plurality of physical blocks in units of pages. The controller circuit is also configured to execute a first process on the plurality of physical blocks by performing a second process of reading and a third process of data verification on a first page across each of the plurality of physical blocks and then performing the second process of reading and the third process of data verification on a second page across each of the plurality of physical blocks.

Abstract: A memory system includes a non-volatile memory and a controller. The controller is configured to perform an error correction on data read from a memory region of the non-volatile memory, and set a value of a parameter corresponding to a number of parity bits to be added to write data to be written into the memory region based on a number of data bits corrected in the error correction of the read data in a case where the error correction is successful.

Abstract: A memory system includes a nonvolatile memory device and a controller circuit. The nonvolatile memory device includes a plurality of physical blocks, each including a storage area which is accessible in units of pages. The controller circuit is configured to control reading and writing of data which are performed on the plurality of physical blocks in units of pages. The controller circuit is also configured to execute a first process on the plurality of physical blocks by performing a second process of reading and a third process of data verification on a first page across each of the plurality of physical blocks and then performing the second process of reading and the third process of data verification on a second page across each of the plurality of physical blocks.

Abstract: According to one embodiment, there is provided a memory system including a 1st memory group, a 2nd memory group, a power supply voltage adjustment circuit, a 1st line, a 1st switch, a 2nd line, a 3rd line, and a 4th line. The power supply voltage adjustment circuit includes a 1st terminal and a 2nd terminal. The 1st line electrically connects the 1st terminal to the 1st memory group. The 1st switch includes a 3rd terminal, a 4th terminal, and a 5th terminal. The 1st switch electrically connects the 3rd terminal to the 4th terminal when turned on. The 2nd line electrically connects the 1st terminal to the 3rd terminal. The 3rd line electrically connects the 4th terminal to the 2nd memory group. The 4th line electrically connects the 2nd terminal to the 5th terminal.