Abstract: [Problem] A compound useful as an active ingredient of a pharmaceutical composition for treating pancreatic cancer is provided. [Solution] The present inventors have studied about a compound that is useful as an active ingredient of a pharmaceutical composition for treating pancreatic cancer and have found that a 4-aminoquinazoline compound has an excellent G12D mutant KRAS inhibition activity and can be used as a therapeutic agent for pancreatic cancer, thus completing the present invention. The 4-aminoquinazoline compound of the present invention or a salt thereof can be used as a therapeutic agent for pancreatic cancer.

Abstract: A catalyst for purification of exhaust gas in which Pd-based nanoparticles and ceria nanoparticles are supported on a composite metal oxide support containing alumina, ceria, and zirconia, wherein a molar ratio (Ce/Pd) of Ce and Pd supported on the support is 1 to 8, a proximity ? between Pd and Ce is 0.15 to 0.50, wherein the proximity ? is determined, based on Pd and Ce distribution maps in an element mapping image of energy dispersive X-ray analysis, by the following formula (1): ? = ? j = 0 N - 1 ? ? i = 0 M - 1 ? ( ( I ? ( i , j ) - I ave ) ? ( T ? ( i , j ) - T ave ) ) ? j = 0 N - 1 ? ? i = 0 M - 1 ? ( I ? ( i , j ) - I ave ) 2 - ? j = 0 N - 1 ? ? i = 0 M - 1 ? ( T ? ( i , j ) - T ave ) 2 , ( 1 ) a Pd dispersity after a heat-resistance test at 1050° C. for 25 hours is 0.8% or more.

Abstract: Provided is a semiconductor device where an electric field applied to an electric field protection layer at a bottom of a trench gate electrode of an active region is relaxed and an avalanche withstand voltage is improved. The semiconductor device includes: an active region that has multiple gate trenches, a trench gate electrode in each gate trench, and a P body layer provided to a section other than the gate trenches; and a termination region disposed on the outer periphery of the active region. Additionally, an electric field protection layer is provided to the bottom of each gate trench of the active region, an electric field relaxation layer is between the active region and the termination region, the bottom surface of the electric field relaxation layer is shallower than that of the electric field protection layer, and the electric field relaxation layer is electrically connected to the P body layer.

Abstract: A work coordinate generation device includes a shape register section configured to register shape information about a shape of a work region optically defined on a target which is a work target of a work robot; a first recognition section configured to acquire first image data; a first coordinate generation section configured to generate a first work coordinate which represents the work region of the first target based on a result of recognition of the first recognition section; a second recognition section configured to acquire second image data; and a second coordinate generation section configured to generate a second work coordinate which represents the work region of the second target based on the first work coordinate and a result of recognition of the second recognition section.

Abstract: A work coordinate generation device includes a shape register section configured to register shape information about a shape of a work region optically defined on a target which is a work target of a work robot; a first recognition section configured to acquire first image data; a first coordinate generation section configured to generate a first work coordinate which represents the work region of the first target based on a result of recognition of the first recognition section; a second recognition section configured to acquire second image data; and a second coordinate generation section configured to generate a second work coordinate which represents the work region of the second target based on the first work coordinate and a result of recognition of the second recognition section.

Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

Abstract: A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.

Abstract: A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

Abstract: A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.

Abstract: A method of processing a substrate includes: growing a first layer including a first element and a second element by supplying a first precursor containing the first element and a second precursor containing the second element to the substrate; and growing a second layer including the second element and a third element by supplying the second precursor and a third precursor containing the third element to the substrate. The act of growing the first layer and the act of growing the second layer are alternately performed a predetermined number of times, and the act of growing the first layer is performed before the act of growing the second layer to selectively grow a laminated film on a conductive film exposed on the surface of the substrate. The first layer and the second layer are laminated to form the laminated film.

Abstract: An aircraft communication system for performing communication between each of a plurality of devices installed in an aircraft, wherein the communication system is provided with a plurality of communication processing units provided corresponding to the plurality of devices and a plurality of communication lines for connecting between the communication processing units, the plurality of communication processing units being capable of bidirectional communication via the plurality of communication lines. Upon receiving a plurality of communication data from the plurality of communication lines, one of the communication processing units determines, on the basis of identification information included in the received plurality of communication data, whether the received plurality of communication data needs to be acquired and acquires the communication data determined to need to be acquired.

Abstract: A method of processing a substrate includes: growing a first layer including a first element and a second element by supplying a first precursor containing the first element and a second precursor containing the second element to the substrate; and growing a second layer including the second element and a third element by supplying the second precursor and a third precursor containing the third element to the substrate. The act of growing the first layer and the act of growing the second layer are alternately performed a predetermined number of times, and the act of growing the first layer is performed before the act of growing the second layer to selectively grow a laminated film on a conductive film exposed on the surface of the substrate. The first layer and the second layer are laminated to form the laminated film.

Abstract: An aircraft communication system for performing communication between each of a plurality of devices installed in an aircraft, wherein the communication system is provided with a plurality of communication processing units provided corresponding to the plurality of devices and a plurality of communication lines for connecting between the communication processing units, the plurality of communication processing units being capable of bidirectional communication via the plurality of communication lines. Upon receiving a plurality of communication data from the plurality of communication lines, one of the communication processing units determines, on the basis of identification information included in the received plurality of communication data, whether the received plurality of communication data needs to be acquired and acquires the communication data determined to need to be acquired.

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract: An object of the present invention is to provide a technique for suppressing thermal disturbance of a phase change memory device having a three-dimensional structure. In the phase change memory device having a three-dimensional structure, a material having a high thermal conductivity is used as a gate insulation film of a MOS transistor for selection, and causes heat transmitted to a Si channel layer from a phase change recording film to successfully diffuse to a gate electrode. In this way, since heat generated from a recording bit diffuses to a non-selected bit adjacent to it, it is possible to suppress thermal disturbance. BN, Al2O3, AlN, TiO2, Si3N4, ZnO and the like are useful as a gate insulation film having a high thermal conductivity.

Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract: A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Abstract: A technique capable of improving performances of a semiconductor memory device provided with a recording film having a super lattice structure is provided. The semiconductor memory device records information by changing an electric resistance of a recording film by use of a change in an atomic arrangement of the recording film. Moreover, the recording film is provided with a stacked layer portion in which a first crystal layer and a second crystal layer made of chalcogen compounds having respectively different compositions are stacked, an orientation layer that enhances an orientation of the stacked layer portion, and an adhesive layer that improves the flatness of the orientation layer.

Abstract: A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of Sb2Te3 and GeTe. The phase change memory layer having the superlattice structure includes a Sb2Te3 layer containing Zr in contact with the first electrode.